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| author | yufeng <yufeng@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-01-17 14:27:36 +0000 |
|---|---|---|
| committer | yufeng <yufeng@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-01-17 14:27:36 +0000 |
| commit | ee4d7d9ed7a868e4e20f1816f802843ae7685d54 (patch) | |
| tree | f129a6ce4913ae778276244dc933a383a232aa46 /libgcc | |
| parent | 3f442959db155a0ef27112734f7183aacbdec95d (diff) | |
| download | ppe42-gcc-ee4d7d9ed7a868e4e20f1816f802843ae7685d54.tar.gz ppe42-gcc-ee4d7d9ed7a868e4e20f1816f802843ae7685d54.zip | |
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Cast the
results of (dcache_lsize - 1) and (icache_lsize - 1) to the type
__UINTPTR_TYPE__; also cast 'base' to the same type before the
alignment operation.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@195266 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libgcc')
| -rw-r--r-- | libgcc/ChangeLog | 7 | ||||
| -rw-r--r-- | libgcc/config/aarch64/sync-cache.c | 6 |
2 files changed, 11 insertions, 2 deletions
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 77504494477..d47f64ebb5f 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,10 @@ +2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> + + * config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Cast the + results of (dcache_lsize - 1) and (icache_lsize - 1) to the type + __UINTPTR_TYPE__; also cast 'base' to the same type before the + alignment operation. + 2013-01-15 Sofiane Naci <sofiane.naci@arm.com> * config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Update diff --git a/libgcc/config/aarch64/sync-cache.c b/libgcc/config/aarch64/sync-cache.c index 2512cb8e87e..66b7afedc1f 100644 --- a/libgcc/config/aarch64/sync-cache.c +++ b/libgcc/config/aarch64/sync-cache.c @@ -40,7 +40,8 @@ __aarch64_sync_cache_range (const void *base, const void *end) as per the GNU definition of __clear_cache. */ /* Make the start address of the loop cache aligned. */ - address = (const char*) ((unsigned long) base & ~ (dcache_lsize - 1)); + address = (const char*) ((__UINTPTR_TYPE__) base + & ~ (__UINTPTR_TYPE__) (dcache_lsize - 1)); for (address; address < (const char *) end; address += dcache_lsize) asm volatile ("dc\tcvau, %0" @@ -51,7 +52,8 @@ __aarch64_sync_cache_range (const void *base, const void *end) asm volatile ("dsb\tish" : : : "memory"); /* Make the start address of the loop cache aligned. */ - address = (const char*) ((unsigned long) base & ~ (icache_lsize - 1)); + address = (const char*) ((__UINTPTR_TYPE__) base + & ~ (__UINTPTR_TYPE__) (icache_lsize - 1)); for (address; address < (const char *) end; address += icache_lsize) asm volatile ("ic\tivau, %0" |
