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| author | wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-09-20 21:42:25 +0000 |
|---|---|---|
| committer | wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-09-20 21:42:25 +0000 |
| commit | 91cf636e41311e5f7010a6dd2dbd0da8209f5930 (patch) | |
| tree | 4153c004242ecb1aee635758e2f6c7141a996b18 /gcc | |
| parent | ebeaf10cba64b5cd57393f855d2bb8ffadbc79f1 (diff) | |
| download | ppe42-gcc-91cf636e41311e5f7010a6dd2dbd0da8209f5930.tar.gz ppe42-gcc-91cf636e41311e5f7010a6dd2dbd0da8209f5930.zip | |
Fix v850 ICE.
* combine.c (try_combine): When split an instruction pair, where the
first has a sign_extend src, verify that the src and dest modes match.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@57371 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/combine.c | 6 |
2 files changed, 11 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d28402f9a32..103bc9468ba 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2002-09-20 Jim Wilson <wilson@redhat.com> + + * combine.c (try_combine): When split an instruction pair, where the + first has a sign_extend src, verify that the src and dest modes match. + 2002-09-20 Richard Henderson <rth@redhat.com> * config/mips/mips.c (dfhigh, dflow, sfhigh, sflow): Remove. diff --git a/gcc/combine.c b/gcc/combine.c index 23136194bf0..1d6a5b270b7 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -2316,6 +2316,10 @@ try_combine (i3, i2, i1, new_direct_jump_p) copy. This saves at least one insn, more if register allocation can eliminate the copy. + We cannot do this if the destination of the first assignment is a + condition code register or cc0. We eliminate this case by making sure + the SET_DEST and SET_SRC have the same mode. + We cannot do this if the destination of the second assignment is a register that we have already assumed is zero-extended. Similarly for a SUBREG of such a register. */ @@ -2325,6 +2329,8 @@ try_combine (i3, i2, i1, new_direct_jump_p) && XVECLEN (newpat, 0) == 2 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND + && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) + == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) && GET_CODE (XVECEXP (newpat, 0, 1)) == SET && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) |
