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author | ebotcazou <ebotcazou@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-01-27 13:29:26 +0000 |
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committer | ebotcazou <ebotcazou@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-01-27 13:29:26 +0000 |
commit | 8721ac359690b9d29d4d7571524a844b0a03416a (patch) | |
tree | 8612898897c739a2f1db954d9170d5f3ca646417 /gcc | |
parent | 08d163a9f560aba0131e1ec71cc5de397c8579fb (diff) | |
download | ppe42-gcc-8721ac359690b9d29d4d7571524a844b0a03416a.tar.gz ppe42-gcc-8721ac359690b9d29d4d7571524a844b0a03416a.zip |
PR target/10904
PR target/13058
* config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): New.
Forbid mode changes from SImode for lower FP regs if ARCH64.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@76702 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/config/sparc/sparc.h | 14 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/20040127-1.c | 24 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/20040127-2.c | 32 |
5 files changed, 82 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1e5bfa2f723..60d2990a6a6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2004-01-27 Eric Botcazou <ebotcazou@libertysurf.fr> + + PR target/10904 + PR target/13058 + * config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): New. + Forbid mode changes from SImode for lower FP regs if ARCH64. + 2004-01-27 J"orn Rennecke <joern.rennecke@superh.com> * Makefile.in (bt-load.o): Depend on except.h. diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 06fd5ee328a..eeab3c6a7fd 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1264,6 +1264,20 @@ enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ {-1, -1, -1, 0x3f}} /* ALL_REGS */ +/* Defines invalid mode changes. Borrowed from pa64-regs.h. + + SImode loads to floating-point registers are not zero-extended. + The definition for LOAD_EXTEND_OP specifies that integer loads + narrower than BITS_PER_WORD will be zero-extended. As a result, + we inhibit changes from SImode unless they are to a mode that is + identical in size. */ + +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (TARGET_ARCH64 \ + && (FROM) == SImode \ + && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) + /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 273fb4295e2..475dd337b66 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2004-01-27 Eric Botcazou <ebotcazou@libertysurf.fr> + + * gcc.dg/20040127-1.c: New test. + * gcc.dg/20040127-2.c: New test. + 2004-01-26 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE> * objc.dg/stret-1.m (glob): Renamed to globa. diff --git a/gcc/testsuite/gcc.dg/20040127-1.c b/gcc/testsuite/gcc.dg/20040127-1.c new file mode 100644 index 00000000000..0ea6062a5a9 --- /dev/null +++ b/gcc/testsuite/gcc.dg/20040127-1.c @@ -0,0 +1,24 @@ +/* PR target/10904 */ +/* Origin: <kminola@eng.umd.edu> */ + +/* Verify that the register allocator correctly aligns + floating-point registers on SPARC64. */ + +/* { dg-do assemble } */ +/* { dg-options "-O2" } */ + +extern int foo1(); +extern int foo2(); + +void foo(int n, int b) +{ + int i, a; + + foo1(); + + a = (long)(b * ((double) 0.1)); + + for (i=0; i < n; i++) { + foo2(a); + } +} diff --git a/gcc/testsuite/gcc.dg/20040127-2.c b/gcc/testsuite/gcc.dg/20040127-2.c new file mode 100644 index 00000000000..6e56dd8fc10 --- /dev/null +++ b/gcc/testsuite/gcc.dg/20040127-2.c @@ -0,0 +1,32 @@ +/* PR target/13058 */ +/* Origin: Lloyd Parkes <lloyd@must-have-coffee.gen.nz> */ +/* Reduced testcase by Falk Hueffner <falk@debian.org> */ + +/* Verify that the register allocator correctly aligns + floating-point registers on SPARC64. */ + +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +typedef struct { int ThumbnailSize; } ImageInfo_t; + +double ConvertAnyFormat(void) +{ + return 0; +} + +void ProcessExifDir(ImageInfo_t *ImageInfoP, int NumDirEntries) +{ + unsigned int ThumbnailSize; + + for (; NumDirEntries;) { + Get16u(); + switch (NumDirEntries) { + case 0x0201: + case 0x0202: + ThumbnailSize = ConvertAnyFormat(); + } + } + + ImageInfoP->ThumbnailSize = ThumbnailSize; +} |