diff options
| author | falk <falk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-05-01 12:26:28 +0000 |
|---|---|---|
| committer | falk <falk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-05-01 12:26:28 +0000 |
| commit | 6399d209afaffd748232b9fa48dda2a4435e8ec8 (patch) | |
| tree | 2119dd813dbb9bfae4d15e5f7ba881b226d9b7e3 /gcc | |
| parent | be8c6d9ccec1640aa1b7e55aeac8fd744509dc88 (diff) | |
| download | ppe42-gcc-6399d209afaffd748232b9fa48dda2a4435e8ec8.tar.gz ppe42-gcc-6399d209afaffd748232b9fa48dda2a4435e8ec8.zip | |
* config/alpha/alpha.md (builtin_insbl, builtin_inswl,
builtin_insll): Disallow 0 as first input operand.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@81387 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d442d303fd5..2b79a6c0f1e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2004-05-01 Falk Hueffner <falk@debian.org> + * config/alpha/alpha.md (builtin_insbl, builtin_inswl, + builtin_insll): Disallow 0 as first input operand. + +2004-05-01 Falk Hueffner <falk@debian.org> + * config/alpha/alpha.c (alpha_rtx_costs): Fix shiftadd costs. 2004-05-01 Ulrich Weigand <uweigand@de.ibm.com> diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 64c88e32332..3d3b7313cc7 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -7185,7 +7185,7 @@ (define_expand "builtin_insbl" [(match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" "")] "" { @@ -7201,7 +7201,7 @@ (define_expand "builtin_inswl" [(match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" "")] "" { @@ -7217,7 +7217,7 @@ (define_expand "builtin_insll" [(match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" "")] "" { |
