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| author | kenner <kenner@138bc75d-0d04-0410-961f-82ee72b054a4> | 1995-05-16 12:14:26 +0000 |
|---|---|---|
| committer | kenner <kenner@138bc75d-0d04-0410-961f-82ee72b054a4> | 1995-05-16 12:14:26 +0000 |
| commit | 01cc3b7526f036bef25d4140ef0903276a67aa9a (patch) | |
| tree | bf405c4941b111c08c0642d3410b2970aca3b162 /gcc | |
| parent | 6a63b8ac07f1b0e513c0b549c074e71c63041c1a (diff) | |
| download | ppe42-gcc-01cc3b7526f036bef25d4140ef0903276a67aa9a.tar.gz ppe42-gcc-01cc3b7526f036bef25d4140ef0903276a67aa9a.zip | |
Fix typos in comments.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@9711 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
81 files changed, 202 insertions, 203 deletions
diff --git a/gcc/bc-emit.c b/gcc/bc-emit.c index c8d50bb7ebc..afadd04cfeb 100644 --- a/gcc/bc-emit.c +++ b/gcc/bc-emit.c @@ -441,7 +441,7 @@ bc_initialize () /* External addresses referenced in a function. Rather than trying to work relocatable address directly into bytecoded functions (which would require us to provide hairy location info and possibly obey alignment - rules imposed by the architecture) we build an auxilary table of + rules imposed by the architecture) we build an auxiliary table of pointer constants, and encode just offsets into this table into the actual bytecode. */ static struct bc_seg *ptrconsts; diff --git a/gcc/bi-lexer.c b/gcc/bi-lexer.c index 0766b5ff953..3391ca6ee56 100644 --- a/gcc/bi-lexer.c +++ b/gcc/bi-lexer.c @@ -26,7 +26,7 @@ static char *buffer = NULL; static char *inpoint = NULL; -/* Safely allocate NBYTES bytes of memory. Reuturns pointer to block of +/* Safely allocate NBYTES bytes of memory. Returns pointer to block of memory. */ static char * diff --git a/gcc/bi-run.h b/gcc/bi-run.h index d7a547d17cd..9b80ea9ddc0 100644 --- a/gcc/bi-run.h +++ b/gcc/bi-run.h @@ -101,7 +101,7 @@ struct bytecode The above applies to BYTE_LOW_ENDIAN machines. In BYTE_BIG_ENDIAN machines, the bit numbering is reversed (i.e. bit 0 is the sign bit). - (Alright, so I drew this to keep my tongue in cheek while writing the code below, + (All right, so I drew this to keep my tongue in cheek while writing the code below, not because I'm into ASCII art.) */ diff --git a/gcc/c-decl.c b/gcc/c-decl.c index f06be296d8f..2c959f6a601 100644 --- a/gcc/c-decl.c +++ b/gcc/c-decl.c @@ -3553,7 +3553,7 @@ start_decl (declarator, declspecs, initialized, attributes, prefix_attributes) TEM may equal DECL or it may be a previous decl of the same name. */ tem = pushdecl (decl); - /* For C and Obective-C, we by default put things in .common when + /* For C and Objective-C, we by default put things in .common when possible. */ DECL_COMMON (tem) = 1; @@ -3809,7 +3809,7 @@ finish_decl (decl, init, asmspec_tree) { preserve_initializer (); /* Hack? Set the permanent bit for something that is permanent, - but not on the permenent obstack, so as to convince + but not on the permanent obstack, so as to convince output_constant_def to make its rtl on the permanent obstack. */ TREE_PERMANENT (DECL_INITIAL (decl)) = 1; diff --git a/gcc/c-iterate.c b/gcc/c-iterate.c index 99f9a794d2a..23b1107cfd6 100644 --- a/gcc/c-iterate.c +++ b/gcc/c-iterate.c @@ -341,7 +341,7 @@ iterator_loop_epilogue (idecl, start_note, end_note) ITERATOR_BOUND_P (idecl) = 0; /* we can reset rtl since there is not chance that this expansion */ - /* would be superceded by a higher level one */ + /* would be superseded by a higher level one */ if (top_level_ixpansion_p ()) DECL_RTL (idecl) = 0; if (end_note) @@ -433,7 +433,7 @@ pop_iterator_stack () /* Record an iterator expansion ("ixpansion") for IDECL. - The remaining paramters are the notes in the loop entry + The remaining parameters are the notes in the loop entry and exit rtl. */ static void diff --git a/gcc/c-lex.c b/gcc/c-lex.c index 2c10890ed0c..a7a2687e006 100644 --- a/gcc/c-lex.c +++ b/gcc/c-lex.c @@ -994,7 +994,7 @@ yylex () goto string_constant; } ungetc(c, finput); - /* Fall through to treat '@' as the start of an indentifier. */ + /* Fall through to treat '@' as the start of an identifier. */ } case 'A': case 'B': case 'C': case 'D': case 'E': diff --git a/gcc/c-parse.in b/gcc/c-parse.in index 25f50f751d3..76c9670fdb0 100644 --- a/gcc/c-parse.in +++ b/gcc/c-parse.in @@ -814,7 +814,7 @@ string: ; ifobjc -/* Produces an OBJC_STRING_CST with prehaps more OBJC_STRING_CSTs chained +/* Produces an OBJC_STRING_CST with perhaps more OBJC_STRING_CSTs chained onto it. */ objc_string: OBJC_STRING @@ -1164,7 +1164,7 @@ initelt: | error /* These are for labeled elements. The syntax for an array element initializer conflicts with the syntax for an Objective-C message, - so don't include these productions in the Objective-C grammer. */ + so don't include these productions in the Objective-C grammar. */ ifc | '[' expr_no_commas ELLIPSIS expr_no_commas ']' '=' { set_init_index ($2, $4); } diff --git a/gcc/c-typeck.c b/gcc/c-typeck.c index 9ac1cad26c4..93a345edc56 100644 --- a/gcc/c-typeck.c +++ b/gcc/c-typeck.c @@ -4921,7 +4921,7 @@ static tree constructor_fields; static tree constructor_index; /* For an ARRAY_TYPE, this is the end index of the range - to intitialize with the next element, or NULL in the ordinary case + to initialize with the next element, or NULL in the ordinary case where the element is used just once. */ static tree constructor_range_end; diff --git a/gcc/calls.c b/gcc/calls.c index 24721f0f696..4d4859275cd 100644 --- a/gcc/calls.c +++ b/gcc/calls.c @@ -161,7 +161,7 @@ calls_function_1 (exp, which) int type = TREE_CODE_CLASS (code); int length = tree_code_length[(int) code]; - /* If this code is langauge-specific, we don't know what it will do. */ + /* If this code is language-specific, we don't know what it will do. */ if ((int) code >= NUM_TREE_CODES) return 1; @@ -1757,7 +1757,7 @@ expand_call (exp, target, ignore) args[i].aligned_regs = (rtx *) alloca (sizeof (rtx) * args[i].n_aligned_regs); - /* Structures smaller than a word are aligned to the least signifcant + /* Structures smaller than a word are aligned to the least significant byte (to the right). On a BYTES_BIG_ENDIAN machine, this means we must skip the empty high order bytes when calculating the bit offset. */ diff --git a/gcc/cccp.c b/gcc/cccp.c index fa1557215b7..e6870cd4a79 100644 --- a/gcc/cccp.c +++ b/gcc/cccp.c @@ -320,7 +320,7 @@ extern const char *const sys_errlist[]; #else extern char *sys_errlist[]; #endif -#else /* HAVE_STERRROR */ +#else /* HAVE_STRERROR */ char *strerror (); #endif #else /* VMS */ @@ -10308,7 +10308,7 @@ fopen (fname, type) #undef fopen /* Get back the REAL fopen routine */ /* The gcc-vms-1.42 distribution's header files prototype fopen with two fixed arguments, which matches ANSI's specification but not VAXCRTL's - pre-ANSI implmentation. This hack circumvents the mismatch problem. */ + pre-ANSI implementation. This hack circumvents the mismatch problem. */ FILE *(*vmslib_fopen)() = (FILE *(*)()) fopen; if (*type == 'w') diff --git a/gcc/collect2.c b/gcc/collect2.c index f991aab36cc..c2a073e6ef7 100644 --- a/gcc/collect2.c +++ b/gcc/collect2.c @@ -190,7 +190,7 @@ char *strerror(); /* Some systems use __main in a way incompatible with its use in gcc, in these cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to give the same symbol without quotes for an alternative entry point. You - must define both, or niether. */ + must define both, or neither. */ #ifndef NAME__MAIN #define NAME__MAIN "__main" #define SYMBOL__MAIN __main diff --git a/gcc/combine.c b/gcc/combine.c index 3b58b34b854..c84549d4193 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -120,7 +120,7 @@ static int combine_successes; static int total_attempts, total_merges, total_extras, total_successes; -/* Define a defulat value for REVERSIBLE_CC_MODE. +/* Define a default value for REVERSIBLE_CC_MODE. We can never assume that a condition code mode is safe to reverse unless the md tells us so. */ #ifndef REVERSIBLE_CC_MODE @@ -2426,7 +2426,7 @@ find_split_point (loc, insn) /* If we have a PLUS whose second operand is a constant and the address is not valid, perhaps will can split it up using the machine-specific way to split large constants. We use - the first psuedo-reg (one of the virtual regs) as a placeholder; + the first pseudo-reg (one of the virtual regs) as a placeholder; it will not remain in the result. */ if (GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT @@ -6163,7 +6163,7 @@ if_then_else_cond (x, ptrue, pfalse) } /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would - make can't possibly match and would supress other optimizations. */ + make can't possibly match and would suppress other optimizations. */ else if (code == COMPARE) ; @@ -10013,7 +10013,7 @@ get_last_value (x) value = SET_SRC (set); /* Make sure that VALUE doesn't reference X. Replace any - expliit references with a CLOBBER. If there are any remaining + explicit references with a CLOBBER. If there are any remaining references (rare), don't use the value. */ if (reg_mentioned_p (x, value)) @@ -10101,7 +10101,7 @@ static int reg_dead_flag; /* Function called via note_stores from reg_dead_at_p. - If DEST is within [reg_dead_rengno, reg_dead_endregno), set + If DEST is within [reg_dead_regno, reg_dead_endregno), set reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ static void diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md index fc566904449..2ab053d2382 100644 --- a/gcc/config/1750a/1750a.md +++ b/gcc/config/1750a/1750a.md @@ -949,7 +949,7 @@ ;******************** ;; Bit field instructions, general cases. -;; "o,d" constraint causes a nonoffsetable memref to match the "o" +;; "o,d" constraint causes a nonoffsettable memref to match the "o" ;; so that its address is reloaded. ;; (define_insn "extv" ... diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 625c933878a..5c94cdd7c46 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -1318,7 +1318,7 @@ output_prolog (file, size) linked to procedure descriptors. Outputting the lineno helps debugging of one line functions as they would otherwise get no line number at all. Please note that we would - like to put out last_linenum from final.c, but it is not accesible. */ + like to put out last_linenum from final.c, but it is not accessible. */ if (write_symbols == SDB_DEBUG) { diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index ef0f3e146a3..d0f8daf45db 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -552,7 +552,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, /* Loading and storing HImode or QImode values to and from memory usually requires a scratch register. The exceptions are loading QImode and HImode from an aligned address to a general register. - We also cannot load an unaligned address or a paradodixal SUBREG into an + We also cannot load an unaligned address or a paradoxical SUBREG into an FP register. */ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ @@ -942,7 +942,7 @@ extern char *alpha_function_name; /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. Under OSF/1, profiling is enabled - by simply passing -pg to the assember and linker. */ + by simply passing -pg to the assembler and linker. */ #define FUNCTION_PROFILER(FILE, LABELNO) diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index aa745abb6f3..5ec06c8c69a 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -3558,7 +3558,7 @@ { extern rtx get_unaligned_address (); rtx addr = get_unaligned_address (operands[1]); /* It is possible that one of the registers we got for operands[2] - might co-incide with that of operands[0] (which is why we made + might coincide with that of operands[0] (which is why we made it TImode). Pick the other one to use as our scratch. */ rtx scratch = gen_rtx (REG, DImode, REGNO (operands[0]) == REGNO (operands[2]) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 181f1b02f3d..0121d0ec38c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -59,7 +59,7 @@ int arm_compare_fp; /* What type of cpu are we compiling for? */ enum processor_type arm_cpu; -/* Waht type of floating point are we compiling for? */ +/* What type of floating point are we compiling for? */ enum floating_point_type arm_fpu; /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we @@ -2425,7 +2425,7 @@ shift_op (op, amountp) multiplication by a power of 2 with the recognizer for a shift. >=32 is not a valid shift for "asl", so we must try and output a shift that produces the correct arithmetical result. - Using lsr #32 is idendical except for the fact that the carry bit + Using lsr #32 is identical except for the fact that the carry bit is not set correctly if we set the flags; but we never use the carry bit from such an operation, so we can ignore that. */ if (code == ROTATERT) @@ -3038,7 +3038,7 @@ arm_expand_prologue () if (live_regs_mask) { /* If we have to push any regs, then we must push lr as well, or - we won't get a propper return. */ + we won't get a proper return. */ live_regs_mask |= 0x4000; emit_multi_reg_push (live_regs_mask); } @@ -3075,13 +3075,13 @@ arm_expand_prologue () /* If CODE is 'd', then the X is a condition operand and the instruction should only be executed if the condition is true. - if CODE is 'D', then the X is a condition operand and the instruciton + if CODE is 'D', then the X is a condition operand and the instruction should only be executed if the condition is false: however, if the mode of the comparison is CCFPEmode, then always execute the instruction -- we do this because in these circumstances !GE does not necessarily imply LT; in these cases the instruction pattern will take care to make sure that an instruction containing %d will follow, thereby undoing the effects of - doing this instrucion unconditionally. + doing this instruction unconditionally. If CODE is 'N' then X is a floating point operand that must be negated before output. If CODE is 'B' then output a bitwise inverted value of X (a const int). @@ -3320,7 +3320,7 @@ output_load_symbol (insn, operands) abort (); /* When generating the instructions, we never mask out the bits that we - think will be always zero, then if a mistake has occured somewhere, the + think will be always zero, then if a mistake has occurred somewhere, the assembler will spot it and generate an error. */ /* If the symbol is word aligned then we might be able to reduce the @@ -3522,7 +3522,7 @@ final_prescan_insn (insn, opvec, noperands) if (GET_CODE (insn) != JUMP_INSN) return; - /* This jump might be paralled with a clobber of the condition codes + /* This jump might be paralleled with a clobber of the condition codes the jump should always come first */ if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) body = XVECEXP (body, 0, 0); @@ -3740,7 +3740,7 @@ final_prescan_insn (insn, opvec, noperands) } /* restore recog_operand (getting the attributes of other insns can destroy this array, but final.c assumes that it remains intact - accross this call; since the insn has been recognized already we + across this call; since the insn has been recognized already we call recog direct). */ recog (PATTERN (insn), insn, NULL_PTR); } diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index cd783f4fefb..6241a20115d 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1278,7 +1278,7 @@ do \ #define MEMORY_MOVE_COST(MODE) 10 /* All address computations that can be done are free, but rtx cost returns - the same for practically all of them. So we weight the differnt types + the same for practically all of them. So we weight the different types of address here in the order (most pref first): PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ #define ADDRESS_COST(X) \ @@ -1306,9 +1306,9 @@ do \ /* Condition code information. */ /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, return the mode to be used for the comparison. - CCFPEmode should be used with floating inequalites, + CCFPEmode should be used with floating inequalities, CCFPmode should be used with floating equalities. - CC_NOOVmode should be used with SImode integer equalites + CC_NOOVmode should be used with SImode integer equalities. CCmode should be used otherwise. */ #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4c8717fd4ce..36d5f0697f6 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -54,7 +54,7 @@ ; but are if the branch wasn't taken; the effect is to limit the branch ; elimination scanning. -; NOCOND means that the condition codes are niether altered nor affect the +; NOCOND means that the condition codes are neither altered nor affect the ; output of this insn (define_attr "conds" "use,set,clob,jump_clob,nocond" @@ -2104,7 +2104,7 @@ ;; Operand 1 is the destination address in a register (SImode) ;; In both this routine and the next, we must be careful not to spill -;; a memory address of reg+large_const into a seperate PLUS insn, since this +;; a memory address of reg+large_const into a separate PLUS insn, since this ;; can generate unrecognizable rtl. (define_expand "storehi" @@ -3990,7 +3990,7 @@ ") ;; Don't match these patterns if we can use a conditional compare, since they -;; tell the final prescan branch elimator code that full branch inlining +;; tell the final prescan branch eliminator code that full branch inlining ;; can't be done. (define_insn "" @@ -4227,7 +4227,7 @@ ") ;; Don't match these patterns if we can use a conditional compare, since they -;; tell the final prescan branch elimator code that full branch inlining +;; tell the final prescan branch eliminator code that full branch inlining ;; can't be done. (define_insn "" @@ -4390,7 +4390,7 @@ "" "* /* If we have an operation where (op x 0) is the identity operation and - the condtional operator is LT or GE and we are comparing against zero and + the conditional operator is LT or GE and we are comparing against zero and everything is in registers then we can do this in two instructions */ if (operands[3] == const0_rtx && GET_CODE (operands[7]) != AND @@ -4435,7 +4435,7 @@ "" "* /* If we have an operation where (op x 0) is the identity operation and - the condtional operator is LT or GE and we are comparing against zero and + the conditional operator is LT or GE and we are comparing against zero and everything is in registers then we can do this in two instructions */ if (operands[5] == const0_rtx && GET_CODE (operands[7]) != AND @@ -5306,7 +5306,7 @@ ;; any of our local variables. If we call alloca then this is unsafe ;; since restoring the frame frees the memory, which is not what we want. ;; Sometimes the return might have been targeted by the final prescan: -;; if so then emit a propper return insn as well. +;; if so then emit a proper return insn as well. ;; Unfortunately, if the frame pointer is required, we don't know if the ;; current function has any implicit stack pointer adjustments that will ;; be restored by the return: we can't therefore do a tail call. @@ -5416,7 +5416,7 @@ ;; and jump direct to the subroutine. On return from the subroutine ;; execution continues at the branch; this avoids a prefetch stall. ;; We use the length attribute (via short_branch ()) to establish whether or -;; not this is possible, this is the same asthe sparc does. +;; not this is possible, this is the same as the sparc does. (define_peephole [(parallel[(call (mem:SI (match_operand:SI 0 "" "i")) diff --git a/gcc/config/arm/riscix.h b/gcc/config/arm/riscix.h index 0b6336455a6..8e60cfdd0b8 100644 --- a/gcc/config/arm/riscix.h +++ b/gcc/config/arm/riscix.h @@ -58,7 +58,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ %{!mbsd:%{!mxopen:%{!ansi: -D_BSD_C}}}" #endif -/* RISCiX has some wierd symbol name munging, that is done to the object module +/* RISCiX has some weird symbol name munging, that is done to the object module after assembly, which enables multiple libraries to be supported within one (possibly shared) library. It basically changes the symbol name of certain symbols (for example _bcopy is converted to _$bcopy if using BSD) diff --git a/gcc/config/arm/riscix1-1.h b/gcc/config/arm/riscix1-1.h index f6ceeaedb1e..826ec2f93f2 100644 --- a/gcc/config/arm/riscix1-1.h +++ b/gcc/config/arm/riscix1-1.h @@ -74,7 +74,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Some systems use __main in a way incompatible with its use in gcc, in these cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to give the same symbol without quotes for an alternative entry point. You - must define both, or niether. */ + must define both, or neither. */ #ifndef NAME__MAIN #define NAME__MAIN "__gccmain" #define SYMBOL__MAIN __gccmain diff --git a/gcc/config/clipper/clipper.h b/gcc/config/clipper/clipper.h index d0434f8831c..831fec90af5 100644 --- a/gcc/config/clipper/clipper.h +++ b/gcc/config/clipper/clipper.h @@ -127,7 +127,7 @@ extern int target_flags; /* Let's keep the stack somewhat aligned. */ #define STACK_BOUNDARY 64 -/* Define this macro if it is advisible to hold scalars in registers +/* Define this macro if it is advisable to hold scalars in registers in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared type, but kept valid in the wider mode. The signedness of the diff --git a/gcc/config/clipper/clipper.md b/gcc/config/clipper/clipper.md index 50104bf81de..3ccc8d7fef8 100644 --- a/gcc/config/clipper/clipper.md +++ b/gcc/config/clipper/clipper.md @@ -59,7 +59,7 @@ (const_string "clobber"))) ;; -;; clipper seems to be a tradional risc processor +;; clipper seems to be a traditional risc processor ;; we define a functional unit 'memory' ;; (define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0) @@ -305,7 +305,7 @@ operands[1] = force_reg (DImode, operands[1]); }") -;; If an operand is a MEM but not offsetable, we can't load it into +;; If an operand is a MEM but not offsettable, we can't load it into ;; a register, so we must force the third alternative to be the one ;; reloaded. Hence we show the first as more expensive. (define_insn "" diff --git a/gcc/config/dsp16xx/dsp16xx.h b/gcc/config/dsp16xx/dsp16xx.h index 60b507dba48..484a6e44d81 100644 --- a/gcc/config/dsp16xx/dsp16xx.h +++ b/gcc/config/dsp16xx/dsp16xx.h @@ -200,7 +200,7 @@ extern int target_flags; Unit. */ #define TARGET_BMU (target_flags & MASK_BMU) -/* Optimize to conseverve memory */ +/* Optimize to conserve memory */ #define TARGET_OPTIMIZE_MEMORY (target_flags & MASK_OPTIMIZE_MEMORY) /* Optimize for maximum speed */ @@ -330,7 +330,7 @@ extern int target_flags; For the 1600 we can decide arbitrarily since there are no machine instructions for them. */ #define WORDS_BIG_ENDIAN 1 -/* number of bits in an addressible storage unit */ +/* number of bits in an addressable storage unit */ #define BITS_PER_UNIT 16 /* Width in bits of a "word", which is the contents of a machine register. @@ -598,7 +598,7 @@ extern int target_flags; controlled by target switches, then GCC will automatically avoid using these registers when the target switches are opposed to them.) If the user tells us there is no BMU, we can't use - ar0-ar3 for regsiter allocation */ + ar0-ar3 for register allocation */ #define CONDITIONAL_REGISTER_USAGE \ do \ @@ -1159,8 +1159,8 @@ extern struct dsp16xx_frame_info current_frame_info; /* Define the first register to be used for argument passing */ #define FIRST_REG_FOR_FUNCTION_ARG REG_Y -/* Define the profitablity of saving registers around calls. - NOTE: For now we turin this off because of a bug in the +/* Define the profitability of saving registers around calls. + NOTE: For now we turn this off because of a bug in the caller-saves code and also because i'm not sure it is helpful on the 1610. */ @@ -1470,7 +1470,7 @@ extern struct dsp16xx_frame_info current_frame_info; case CONST_DOUBLE: \ return COSTS_N_INSNS (2); -/* Like CONST_COSTS but applies to nonsonstant RTL expressions. +/* Like CONST_COSTS but applies to nonconstant RTL expressions. This can be used, for example to indicate how costly a multiply instruction is. */ #define RTX_COSTS(X,CODE,OUTER_CODE) \ @@ -1896,7 +1896,7 @@ bss_section () \ /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. We should - not have to do any alignemnt since the 1610 is a word machine. */ + not have to do any alignment since the 1610 is a word machine. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) /* Define this macro if ASM_OUTPUT_SKIP should not be used in the text section @@ -1944,8 +1944,8 @@ bss_section () \ /* Defining this macro causes the compiler to omit a sign-extend, zero-extend, or bitwise 'and' instruction that truncates the count of a shift operation to a width equal to the number of bits needed to represent the size of the - object being shifted. Do not define this macro unless the trucation applies - to both shoft operations and bit-field operations (if any). */ + object being shifted. Do not define this macro unless the truncation applies + to both shift operations and bit-field operations (if any). */ /* #define SHIFT_COUNT_TRUNCATED */ /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits diff --git a/gcc/config/dsp16xx/dsp16xx.md b/gcc/config/dsp16xx/dsp16xx.md index 276a12e8b3e..386ad596ea8 100644 --- a/gcc/config/dsp16xx/dsp16xx.md +++ b/gcc/config/dsp16xx/dsp16xx.md @@ -962,8 +962,8 @@ switch (which_alternative) { case 0: - /* We have to use the move mneumonic otherwise the 1610 will - attempt to transfer all 32-bits of 'y', 'p' or an accumualtor + /* We have to use the move mnemonic otherwise the 1610 will + attempt to transfer all 32-bits of 'y', 'p' or an accumulator , which we don't want */ if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD || IS_ACCUM_REG(REGNO(operands[1]))) @@ -1008,8 +1008,8 @@ switch (which_alternative) { case 0: - /* We have to use the move mneumonic otherwise the 1610 will - attempt to transfer all 32-bits of 'y', 'p' or an accumualtor + /* We have to use the move mnemonic otherwise the 1610 will + attempt to transfer all 32-bits of 'y', 'p' or an accumulator , which we don't want */ if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD || IS_ACCUM_REG(REGNO(operands[1]))) diff --git a/gcc/config/elxsi/elxsi.h b/gcc/config/elxsi/elxsi.h index 9ce75ab972a..8007aeb7a69 100644 --- a/gcc/config/elxsi/elxsi.h +++ b/gcc/config/elxsi/elxsi.h @@ -442,7 +442,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; extern int current_function_calls_alloca; \ /* this conditional is ONLY here because there is a BUG; \ EXIT_IGNORE_STACK is ignored itself when the first part of \ - the condition is true! (atleast in version 1.35) */ \ + the condition is true! (at least in version 1.35) */ \ /* the 8*10 is for 64 bits of .r5 - .r14 */ \ if (current_function_calls_alloca || (SIZE)>=(256-8*10)) { \ /* use .r4 as a temporary! Ok for now.... */ \ diff --git a/gcc/config/fp-bit.c b/gcc/config/fp-bit.c index 9f2d27979cf..56984e85f86 100644 --- a/gcc/config/fp-bit.c +++ b/gcc/config/fp-bit.c @@ -435,7 +435,7 @@ unpack_d (FLO_union_type * src, fp_number_type * dst) /* Huge exponent*/ if (fraction == 0) { - /* Attatched to a zero fraction - means infinity */ + /* Attached to a zero fraction - means infinity */ dst->class = CLASS_INFINITY; } else @@ -569,7 +569,7 @@ _fpadd_parts (fp_number_type * a, tmp->normal_exp = a_normal_exp; tmp->fraction.ll = -tfraction; } - /* and renomalize it */ + /* and renormalize it */ while (tmp->fraction.ll < IMPLICIT_1 && tmp->fraction.ll) { diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 6627b10fabf..a14155a03c5 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -869,7 +869,7 @@ print_operand (file, x, code) break; case 'L': /* 'L' must always be used twice in a single pattern. It generates - the same lable twice, and then will generate a unique label the + the same label twice, and then will generate a unique label the next time it is used. */ asm_fprintf (file, "tl%d", (lab++) / 2); break; diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index c1c84e96856..c84d4345e14 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -1629,7 +1629,7 @@ ;; BIT FIELDS ;; ----------------------------------------------------------------- ;; The H8/300 has given 1/8th of its opcode space to bitfield -;; instuctions so let's use them as well as we can +;; instructions so let's use them as well as we can ;; BCC and BCS patterns. diff --git a/gcc/config/i370/i370.h b/gcc/config/i370/i370.h index 1b52ab9cb62..06c5b8835e1 100644 --- a/gcc/config/i370/i370.h +++ b/gcc/config/i370/i370.h @@ -59,7 +59,7 @@ extern int mvs_function_name_length; extern int current_function_outgoing_args_size; -/* Compile using char instructins (mvc, nc, oc, xc). On 4341 use this since +/* Compile using char instructions (mvc, nc, oc, xc). On 4341 use this since these are more than twice as fast as load-op-store. On 3090 don't use this since load-op-store is much faster. */ @@ -94,7 +94,7 @@ extern int current_function_outgoing_args_size; #define WORDS_BIG_ENDIAN 1 -/* Number of bits in an addressible storage unit. */ +/* Number of bits in an addressable storage unit. */ #define BITS_PER_UNIT 8 diff --git a/gcc/config/i370/i370.md b/gcc/config/i370/i370.md index c96b4ab8931..a26c4b4cdca 100644 --- a/gcc/config/i370/i370.md +++ b/gcc/config/i370/i370.md @@ -1,7 +1,7 @@ ;;- Machine description for GNU compiler -- System/370 version. ;; Copyright (C) 1989, 1993, 1994 Free Software Foundation, Inc. ;; Contributed by Jan Stein (jan@cd.chalmers.se). -;; Modifed for MVS C/370 by Dave Pitts (pitts@mcdata.com) +;; Modified for MVS C/370 by Dave Pitts (pitts@mcdata.com) ;; This file is part of GNU CC. @@ -42,7 +42,7 @@ ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)). ;; %X -- Print a constant byte integer in hex. ;; -;; We have a special contraint for pattern matching. +;; We have a special constraint for pattern matching. ;; ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. ;; diff --git a/gcc/config/i370/xm-i370.h b/gcc/config/i370/xm-i370.h index 244da8fba8a..6c3b5d5ccc3 100644 --- a/gcc/config/i370/xm-i370.h +++ b/gcc/config/i370/xm-i370.h @@ -1,7 +1,7 @@ /* Configuration for GNU C-compiler for System/370. Copyright (C) 1989, 1993 Free Software Foundation, Inc. Contributed by Jan Stein (jan@cd.chalmers.se). - Modifed for MVS C/370 by Dave Pitts (pitts@mcdata.com) + Modified for MVS C/370 by Dave Pitts (pitts@mcdata.com) This file is part of GNU CC. diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 1eb56ae92b7..c5f2aa56b72 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -58,7 +58,7 @@ extern int target_flags; /* Macros used in the machine description to test the flags. */ -/* configure can arrage to make this 2, to force a 486. */ +/* configure can arrange to make this 2, to force a 486. */ #ifndef TARGET_CPU_DEFAULT #define TARGET_CPU_DEFAULT 0 #endif @@ -717,7 +717,7 @@ enum reg_class register and zero otherwise. On most machines, this default should be used. Only define this macro to some other expression if pseudo allocated by `local-alloc.c' end up in memory because - their hard registers were needed for spill regisers. If this + their hard registers were needed for spill registers. If this macro returns nonzero for those classes, those pseudos will only be allocated by `global.c', which knows how to reallocate the pseudo to another register. If there would not be another diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h index f17565fd390..1433c2896ee 100644 --- a/gcc/config/i386/linux.h +++ b/gcc/config/i386/linux.h @@ -72,7 +72,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ for x86 FP registers, but the SDB on x86/svr4 is so completely broken with respect to FP registers that it is hardly worth thinking of it as something to strive for compatibility with. - The verison of x86/svr4 SDB I have at the moment does (partially) + The version of x86/svr4 SDB I have at the moment does (partially) seem to believe that DWARF register number 11 is associated with the x86 register %st(0), but that's about all. Higher DWARF register numbers don't seem to be associated with anything in diff --git a/gcc/config/i386/os2.h b/gcc/config/i386/os2.h index 5277019bb15..f6e8ae27e7b 100644 --- a/gcc/config/i386/os2.h +++ b/gcc/config/i386/os2.h @@ -54,7 +54,7 @@ extern int maximum_field_alignment; #undef PCC_BITFIELD_TYPE_MATTERS #define PCC_BITFIELD_TYPE_MATTERS (maximum_field_alignment == 0) -/* Define this macro if it is advisible to hold scalars in registers +/* Define this macro if it is advisable to hold scalars in registers in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared type, but kept valid in the wider mode. The signedness of the diff --git a/gcc/config/i386/sysv4.h b/gcc/config/i386/sysv4.h index 37b612ccf06..97af2a9fc38 100644 --- a/gcc/config/i386/sysv4.h +++ b/gcc/config/i386/sysv4.h @@ -133,7 +133,7 @@ do { long value[3]; \ broken with respect to FP registers that it is hardly worth thinking of it as something to strive for compatibility with. - The verison of x86/svr4 SDB I have at the moment does (partially) + The version of x86/svr4 SDB I have at the moment does (partially) seem to believe that DWARF register number 11 is associated with the x86 register %st(0), but that's about all. Higher DWARF register numbers don't seem to be associated with anything in diff --git a/gcc/config/i860/i860.md b/gcc/config/i860/i860.md index 43cd0fb427b..9544b4cfa22 100644 --- a/gcc/config/i860/i860.md +++ b/gcc/config/i860/i860.md @@ -1441,7 +1441,7 @@ ;; Signed bitfield extractions come out looking like ;; (shiftrt (sign_extend (shift <Y> <C1>)) <C2>) ;; which we expand poorly as four shift insns. -;; These patters yeild two shifts: +;; These patterns yield two shifts: ;; (shiftrt (shift <Y> <C3>) <C4>) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") diff --git a/gcc/config/i860/paragon.h b/gcc/config/i860/paragon.h index 67947988368..e73aa9921de 100644 --- a/gcc/config/i860/paragon.h +++ b/gcc/config/i860/paragon.h @@ -55,7 +55,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* autoinit.o autolaunches NX applications */ #define STARTFILE_SPEC "-ycrt0.o%s %{mnx:-yoptions/autoinit.o%s}" -/* libic.a is the PGI intrisic library */ +/* libic.a is the PGI intrinsic library */ /* libpm.o and guard.o are for the performance monitoring modules (ignored) */ /* /usr/lib/noieee contains non-IEEE compliant (but faster) math routines */ #if HAVE_DASH_G diff --git a/gcc/config/i960/i960.c b/gcc/config/i960/i960.c index 0c64a03bea5..f9ddfec7051 100644 --- a/gcc/config/i960/i960.c +++ b/gcc/config/i960/i960.c @@ -827,7 +827,7 @@ i960_function_name_declare (file, name, fndecl) else leaf_proc_ok = 0; - /* Even if nobody uses extra parms, can't have leafroc or tail calls if + /* Even if nobody uses extra parms, can't have leafproc or tail calls if argblock, because argblock uses g14 implicitly. */ if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl)) diff --git a/gcc/config/i960/i960.h b/gcc/config/i960/i960.h index 226682e927d..6df7e210eab 100644 --- a/gcc/config/i960/i960.h +++ b/gcc/config/i960/i960.h @@ -307,7 +307,7 @@ extern int target_flags; /* Target machine storage layout. */ /* Define for cross-compilation from a host with a different float format - or endianess (e.g. VAX, x86). */ + or endianness (e.g. VAX, x86). */ #define REAL_ARITHMETIC /* Define this if most significant bit is lowest numbered diff --git a/gcc/config/m68k/ccur-GAS.h b/gcc/config/m68k/ccur-GAS.h index 7b90d9d114b..b23001a9238 100644 --- a/gcc/config/m68k/ccur-GAS.h +++ b/gcc/config/m68k/ccur-GAS.h @@ -75,7 +75,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #undef EMPTY_FIELD_BOUNDARY #define EMPTY_FIELD_BOUNDARY 32 -/* Allocation boundry in bits for the code of a function */ +/* Allocation boundary in bits for the code of a function */ #undef FUNCTION_BOUNDARY #define FUNCTION_BOUNDARY 32 diff --git a/gcc/config/m68k/hp320.h b/gcc/config/m68k/hp320.h index 81529767e84..0b47f8ccc9a 100644 --- a/gcc/config/m68k/hp320.h +++ b/gcc/config/m68k/hp320.h @@ -601,6 +601,6 @@ do { register int i; \ (! symbolic_operand (X, VOIDmode) \ || ((GET_CODE(X) == SYMBOL_REF) && SYMBOL_REF_FLAG(X))) -/* hpux8 and later have C++ compatable include files, so do not +/* hpux8 and later have C++ compatible include files, so do not pretend they are `extern "C"'. */ #define NO_IMPLICIT_EXTERN_C diff --git a/gcc/config/m68k/lb1sf68.asm b/gcc/config/m68k/lb1sf68.asm index 922df8f8a3e..7833e5388d2 100644 --- a/gcc/config/m68k/lb1sf68.asm +++ b/gcc/config/m68k/lb1sf68.asm @@ -315,7 +315,7 @@ L4: lsrl IMM (1), d1 /* shift divisor */ divu d1, d0 /* now we have 16 bit divisor */ andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */ -/* Muliply the 16 bit tentative quotient with the 32 bit divisor. Because of +/* Multiply the 16 bit tentative quotient with the 32 bit divisor. Because of the operand ranges, this might give a 33 bit product. If this product is greater than the dividend, the tentative quotient was too large. */ movel d2, d1 @@ -628,7 +628,7 @@ Ladddf$2: | Here we have a's exponent larger than b's, so we have to shift b. We do | this by using as counter d2: 1: movew d4,d2 | move largest exponent to d2 - subw d5,d2 | and substract second exponent + subw d5,d2 | and subtract second exponent exg d4,a2 | get back the longs we saved exg d5,a3 | | if difference is too large we don't shift (actually, we can just exit) ' @@ -714,7 +714,7 @@ Ladddf$4: | Now we have the numbers in d0--d3 and d4--d7, the exponent in a2, and | the signs in a4. -| Here we have to decide whether to add or substract the numbers: +| Here we have to decide whether to add or subtract the numbers: exg d7,a0 | get the signs exg d6,a3 | a3 is free to be used movel d7,d6 | @@ -723,7 +723,7 @@ Ladddf$4: movew IMM (0),d6 | and b's sign in d6 ' eorl d7,d6 | compare the signs bmi Lsubdf$0 | if the signs are different we have - | to substract + | to subtract exg d7,a0 | else we add the numbers exg d6,a3 | addl d7,d3 | @@ -739,7 +739,7 @@ Ladddf$4: | Before rounding normalize so bit #DBL_MANT_DIG is set (we will consider | the case of denormalized numbers in the rounding routine itself). -| As in the addition (not in the substraction!) we could have set +| As in the addition (not in the subtraction!) we could have set | one more bit we check this: btst IMM (DBL_MANT_DIG+1),d0 beq 1f @@ -772,7 +772,7 @@ Ladddf$5: bra Ld$overflow Lsubdf$0: -| Here we do the substraction. +| Here we do the subtraction. exg d7,a0 | put sign back in a0 exg d6,a3 | subl d7,d3 | @@ -796,7 +796,7 @@ Lsubdf$0: | Before rounding normalize so bit #DBL_MANT_DIG is set (we will consider | the case of denormalized numbers in the rounding routine itself). -| As in the addition (not in the substraction!) we could have set +| As in the addition (not in the subtraction!) we could have set | one more bit we check this: btst IMM (DBL_MANT_DIG+1),d0 beq 1f @@ -927,7 +927,7 @@ Ladddf$nf: 3: | Now comes the check for +/-INFINITY. We know that both are (maybe not | finite) numbers, but we have to check if both are infinite whether we -| are adding or substracting them. +| are adding or subtracting them. eorl d7,d6 | to check sign bits bmi 1f andl IMM (0x80000000),d7 | get (common) sign bit @@ -999,7 +999,7 @@ Lmuldf$1: lsrw IMM (4),d5 | Lmuldf$2: | addw d5,d4 | add exponents - subw IMM (D_BIAS+1),d4 | and substract bias (plus one) + subw IMM (D_BIAS+1),d4 | and subtract bias (plus one) | We are now ready to do the multiplication. The situation is as follows: | both a and b have bit 52 ( bit 20 of d0 and d2) set (even if they were @@ -1210,7 +1210,7 @@ Ldivdf$1: | swap d5 | lsrw IMM (4),d5 | Ldivdf$2: | - subw d5,d4 | substract exponents + subw d5,d4 | subtract exponents addw IMM (D_BIAS),d4 | and add bias | We are now ready to do the division. We have prepared things in such a way @@ -1245,7 +1245,7 @@ Ldivdf$2: | dbra d5,1b | and branch back bra 5f 4: cmpl d1,d3 | here d0==d2, so check d1 and d3 - bhi 3b | if d1 > d2 skip the substraction + bhi 3b | if d1 > d2 skip the subtraction bra 2b | else go do it 5: | Here we have to start setting the bits in the second long. @@ -1262,7 +1262,7 @@ Ldivdf$2: | dbra d5,1b | and branch back bra 5f 4: cmpl d1,d3 | here d0==d2, so check d1 and d3 - bhi 3b | if d1 > d2 skip the substraction + bhi 3b | if d1 > d2 skip the subtraction bra 2b | else go do it 5: | Now go ahead checking until we hit a one, which we store in d2. @@ -1902,12 +1902,12 @@ Laddsf$2: | signs are stored in a0 and a1). Laddsf$3: -| Here we have to decide whether to add or substract the numbers +| Here we have to decide whether to add or subtract the numbers exg d6,a0 | get signs back exg d7,a1 | and save the exponents eorl d6,d7 | combine sign bits bmi Lsubsf$0 | if negative a and b have opposite - | sign so we actually substract the + | sign so we actually subtract the | numbers | Here we have both positive or both negative @@ -1926,7 +1926,7 @@ Laddsf$3: | Before rounding normalize so bit #FLT_MANT_DIG is set (we will consider | the case of denormalized numbers in the rounding routine itself). -| As in the addition (not in the substraction!) we could have set +| As in the addition (not in the subtraction!) we could have set | one more bit we check this: btst IMM (FLT_MANT_DIG+1),d0 beq 1f @@ -1957,7 +1957,7 @@ Laddsf$4: Lsubsf$0: | We are here if a > 0 and b < 0 (sign bits cleared). -| Here we do the substraction. +| Here we do the subtraction. movel d6,d7 | put sign in d7 andl IMM (0x80000000),d7 @@ -1974,7 +1974,7 @@ Lsubsf$0: | Now d0-d1 is positive and the sign bit is in d7. -| Note that we do not have to normalize, since in the substraction bit +| Note that we do not have to normalize, since in the subtraction bit | #FLT_MANT_DIG+1 is never set, and denormalized numbers are handled by | the rounding routines themselves. lea Lsubsf$1,a0 | to return from rounding routine @@ -2071,7 +2071,7 @@ Laddsf$ret$den: | Note: when adding two floats of the same sign if either one is | NaN we return NaN without regard to whether the other is finite or -| not. When substracting them (i.e., when adding two numbers of +| not. When subtracting them (i.e., when adding two numbers of | opposite signs) things are more complicated: if both are INFINITY | we return NaN, if only one is INFINITY and the other is NaN we return | NaN, but if it is finite we return INFINITY with the corresponding sign. @@ -2095,7 +2095,7 @@ Laddsf$nf: bhi Lf$inop | Now comes the check for +/-INFINITY. We know that both are (maybe not | finite) numbers, but we have to check if both are infinite whether we -| are adding or substracting them. +| are adding or subtracting them. eorl d3,d2 | to check sign bits bmi 1f movel d0,d7 @@ -2161,7 +2161,7 @@ Lmulsf$1: | number lsrw IMM (7),d3 | Lmulsf$2: | addw d3,d2 | add exponents - subw IMM (F_BIAS+1),d2 | and substract bias (plus one) + subw IMM (F_BIAS+1),d2 | and subtract bias (plus one) | We are now ready to do the multiplication. The situation is as follows: | both a and b have bit FLT_MANT_DIG-1 set (even if they were @@ -2292,7 +2292,7 @@ SYM (__divsf3): beq Ldivsf$b$0 | branch if b is zero cmpl d6,d0 | is a big? bhi Ldivsf$inop | if a is NaN return NaN - beq Ldivsf$inf | if a is INIFINITY we have to check b + beq Ldivsf$inf | if a is INFINITY we have to check b cmpl d6,d1 | now compare b with INFINITY bhi Ldivsf$inop | if b is NaN return NaN beq Ldivsf$underflow @@ -2314,7 +2314,7 @@ Ldivsf$1: | swap d3 | lsrw IMM (7),d3 | Ldivsf$2: | - subw d3,d2 | substract exponents + subw d3,d2 | subtract exponents addw IMM (F_BIAS),d2 | and add bias | We are now ready to do the division. We have prepared things in such a way diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 25211a9335c..95354c34733 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -1040,7 +1040,7 @@ const_method (constant) /* Likewise, try with not.w */ if (use_movq (i ^ 0xffff)) return NOTW; - /* This is the only value where neg.w is usefull */ + /* This is the only value where neg.w is useful */ if (i == -65408) return NEGW; /* Try also with swap */ diff --git a/gcc/config/m68k/plexus.h b/gcc/config/m68k/plexus.h index 2be4158eda3..0bdb05a913f 100644 --- a/gcc/config/m68k/plexus.h +++ b/gcc/config/m68k/plexus.h @@ -15,7 +15,7 @@ The Plexus port of gcc requires you to use gas ( either 1.3X with COFF patches or 2.X ), If you use gas 2.X you have to use binutils-2.X. - With using gas-2.X the Plexus gcc port is now capabable of generating + With using gas-2.X the Plexus gcc port is now capable of generating output suitable for use by gdb-4.X ( send mail to above address for info on getting gdb patches or other GNU items for the Plexus ) diff --git a/gcc/config/m68k/x-apollo68 b/gcc/config/m68k/x-apollo68 index 428d90c1cbe..4c809f958f9 100644 --- a/gcc/config/m68k/x-apollo68 +++ b/gcc/config/m68k/x-apollo68 @@ -6,7 +6,7 @@ CC=cc -g -A nansi -A cpu,3000 -A runtype,bsd4.3 -A systype,any -DSHORT_ENUM_BUG OLDCC=cc -g -A nansi -A cpu,3000 -A runtype,bsd4.3 -A systype,any -DSHORT_ENUM_BUG # This used to redefine CFLAGS and LIBGCC2_CFLAGS to eliminate the unsupported -# -g flag from both macros. This gives an undebugable stage1 compiler which +# -g flag from both macros. This gives an undebuggable stage1 compiler which # is bad, and it also does the wrong thing if we are cross compiling to a # target which does support debugging. There is currently no way to avoid # the -g option that doesn't break something else. diff --git a/gcc/config/m88k/m88k.c b/gcc/config/m88k/m88k.c index 64e7ebc7334..b61b8826e04 100644 --- a/gcc/config/m88k/m88k.c +++ b/gcc/config/m88k/m88k.c @@ -1349,7 +1349,7 @@ real_or_0_operand (op, mode) && op == CONST0_RTX (mode))); } -/* Return true if OP is valid to use in the context of logic aritmethic +/* Return true if OP is valid to use in the context of logic arithmetic on condition codes. */ int @@ -2029,7 +2029,7 @@ m88k_end_epilogue (stream, size) PUT_OCS_FUNCTION_END (stream); /* If the last insn isn't a BARRIER, we must write a return insn. This - should only happen if the function has no prologe and no body. */ + should only happen if the function has no prologue and no body. */ if (GET_CODE (insn) == NOTE) insn = prev_nonnote_insn (insn); if (insn == 0 || GET_CODE (insn) != BARRIER) diff --git a/gcc/config/m88k/tekXD88.h b/gcc/config/m88k/tekXD88.h index 3fc05ec201d..8cdf561e724 100644 --- a/gcc/config/m88k/tekXD88.h +++ b/gcc/config/m88k/tekXD88.h @@ -41,7 +41,7 @@ /* The bundled ld program needs link editor directives which normally reside in /lib/default.ld. We'll pass our own copy during the link - phase because additioal information about extra sections must be added + phase because additional information about extra sections must be added so that gcc generated files will link properly. --KRG. */ diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 9296fdedb15..94a2210285f 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -117,7 +117,7 @@ int num_source_filenames = 0; start and end boundaries). */ int sdb_label_count = 0; -/* Next label # for each statment for Silicon Graphics IRIS systems. */ +/* Next label # for each statement for Silicon Graphics IRIS systems. */ int sym_lineno = 0; /* Non-zero if inside of a function, because the stupid MIPS asm can't @@ -4716,7 +4716,7 @@ save_restore_insns (store_p, large_reg, large_offset, file) } else { - base_reg_rtx = (rtx)0; /* Make sure these are initialzed */ + base_reg_rtx = (rtx)0; /* Make sure these are initialized */ base_offset = 0; } diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index afe25335687..39f6cf39d33 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -3314,7 +3314,7 @@ while (0) #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ mips_output_filename (STREAM, NAME) -/* This is defined so that it can be overriden in iris6.h. */ +/* This is defined so that it can be overridden in iris6.h. */ #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \ do \ { \ diff --git a/gcc/config/nextstep21.h b/gcc/config/nextstep21.h index 14229a5ce68..5c572868999 100644 --- a/gcc/config/nextstep21.h +++ b/gcc/config/nextstep21.h @@ -26,7 +26,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #undef USE_COLLECT2 #define USE_COLLECT2 -/* use this until a newer gdb for NeXTStep21 is availible */ +/* use this until a newer gdb for NeXTStep21 is available */ #define DEFAULT_GDB_EXTENSIONS 0 /* we need the call to __main to start all global destructors and constructors diff --git a/gcc/config/pa/pa-hpux.h b/gcc/config/pa/pa-hpux.h index 10fa503d6b0..43017c74ae2 100644 --- a/gcc/config/pa/pa-hpux.h +++ b/gcc/config/pa/pa-hpux.h @@ -45,6 +45,6 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define LINK_SPEC \ "%{!shared:-u main} %{static:-a archive} %{g*:-a archive} %{shared:-b}" -/* hpux8 and later have C++ compatable include files, so do not +/* hpux8 and later have C++ compatible include files, so do not pretend they are `extern "C"'. */ #define NO_IMPLICIT_EXTERN_C diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 70722cc089f..be95729684a 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -64,7 +64,7 @@ static rtx find_addr_reg (); unsigned int total_code_bytes; /* Variables to handle plabels that we discover are necessary at assembly - output time. They are output after the currrent function. */ + output time. They are output after the current function. */ struct defer_plab { @@ -416,7 +416,7 @@ zdepi_cint_p (x) unsigned HOST_WIDE_INT lsb_mask, t; /* This might not be obvious, but it's at least fast. - This function is critcal; we don't have the time loops would take. */ + This function is critical; we don't have the time loops would take. */ lsb_mask = x & -x; t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); /* Return true iff t is a power of two. */ @@ -619,7 +619,7 @@ legitimize_pic_address (orig, mode, reg) It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed - adressing modes to be used). + addressing modes to be used). Put X and Z into registers. Then put the entire expression into a register. */ @@ -1421,7 +1421,7 @@ output_fp_move_double (operands) output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); } /* This is a pain. You have to be prepared to deal with an - arbritary address here including pre/post increment/decrement. + arbitrary address here including pre/post increment/decrement. so avoid this in the MD. */ else @@ -2225,7 +2225,7 @@ hppa_expand_prologue() mcounts do, _mcount appears to behave differently on the HPPA. It takes the return address of the caller, the address of this routine, and the address of the label. Also, it isn't magic, so - argument registre hsave to be preserved. */ + argument registers have to be preserved. */ if (profile_flag) { int pc_offset, i, arg_offset, basereg, offsetadj; @@ -2657,7 +2657,7 @@ pa_adjust_cost (insn, link, dep_insn, cost) case TYPE_FPSQRTSGL: case TYPE_FPSQRTDBL: /* A fpload can't be issued until one cycle before a - preceeding arithmetic operation has finished if + preceding arithmetic operation has finished if the target of the fpload is any of the sources (or destination) of the arithmetic operation. */ return cost - (pa_cpu_attr == PROCESSOR_700) ? 1 : 2; @@ -2692,7 +2692,7 @@ pa_adjust_cost (insn, link, dep_insn, cost) case TYPE_FPSQRTSGL: case TYPE_FPSQRTDBL: /* An ALU flop can't be issued until two cycles before a - preceeding divide or sqrt operation has finished if + preceding divide or sqrt operation has finished if the target of the ALU flop is any of the sources (or destination) of the divide or sqrt operation. */ return cost - (pa_cpu_attr == PROCESSOR_700) ? 2 : 4; @@ -2738,7 +2738,7 @@ pa_adjust_cost (insn, link, dep_insn, cost) case TYPE_FPSQRTSGL: case TYPE_FPSQRTDBL: /* A fpload can't be issued until one cycle before a - preceeding arithmetic operation has finished if + preceding arithmetic operation has finished if the target of the fpload is the destination of the arithmetic operation. */ return cost - (pa_cpu_attr == PROCESSOR_700) ? 1 : 2; @@ -2773,7 +2773,7 @@ pa_adjust_cost (insn, link, dep_insn, cost) case TYPE_FPSQRTSGL: case TYPE_FPSQRTDBL: /* An ALU flop can't be issued until two cycles before a - preceeding divide or sqrt operation has finished if + preceding divide or sqrt operation has finished if the target of the ALU flop is also the target of of the divide or sqrt operation. */ return cost - (pa_cpu_attr == PROCESSOR_700) ? 2 : 4; @@ -4482,7 +4482,7 @@ jump_in_call_delay (insn) instructions! Because we actually jump into the table, the addresses of each entry - must stay contant in relation to the beginning of the table (which + must stay constant in relation to the beginning of the table (which itself must stay constant relative to the instruction to jump into it). I don't believe we can guarantee earlier passes of the compiler will adhere to those rules. diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 5c94311a54b..8ab2021c7ad 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -155,7 +155,7 @@ extern int target_flags; #define DEFAULT_GDB_EXTENSIONS 1 /* This is the way other stabs-in-XXX tools do things. We will be - compatable. */ + compatible. */ #define DBX_BLOCKS_FUNCTION_RELATIVE 1 /* Likewise for linenos. @@ -180,7 +180,7 @@ extern int target_flags; name *first*... */ #define DBX_FUNCTION_FIRST -/* Only lables should ever begin in colunm zero. */ +/* Only labels should ever begin in column zero. */ #define ASM_STABS_OP "\t.stabs" #define ASM_STABN_OP "\t.stabn" @@ -265,7 +265,7 @@ do { \ /* target machine storage layout */ /* Define for cross-compilation from a host with a different float format - or endianess (e.g. VAX, x86). */ + or endianness (e.g. VAX, x86). */ #define REAL_ARITHMETIC /* Define this macro if it is advisable to hold scalars in registers @@ -1526,7 +1526,7 @@ while (0) /* Arghh. This is used for stuff in the constant pool; this may include function addresses on the PA, which during PIC code generation must - reside in the data space. Unfortuantely, there's no way to determine + reside in the data space. Unfortunately, there's no way to determine if a particular label in the constant pool refers to a function address. So just force everything into the data space during PIC generation. */ #define SELECT_RTX_SECTION(RTX,MODE) \ @@ -1995,7 +1995,7 @@ readonly_data () \ /* This is how to output an element of a case-vector that is relative. This must be defined correctly as it is used when generating PIC code. - I belive it safe to use the same definition as ASM_OUTPUT_ADDR_VEC_ELT + I believe it safe to use the same definition as ASM_OUTPUT_ADDR_VEC_ELT on the PA since ASM_OUTPUT_ADDR_VEC_ELT uses pc-relative jump instructions rather than a table of absolute addresses. */ diff --git a/gcc/config/pa/x-pa b/gcc/config/pa/x-pa index 65d1d6da699..16ef6637f0a 100644 --- a/gcc/config/pa/x-pa +++ b/gcc/config/pa/x-pa @@ -1,4 +1,4 @@ CC=gcc -DUSE_C_ALLOCA -D__inline= -Dbsd4_4 -# BSD on the PA already has ANSI include files which are c++ compatable. +# BSD on the PA already has ANSI include files which are c++ compatible. INSTALL_HEADERS= STMP_FIXPROTO= diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index 96aa14fad27..2d9a2f4e255 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -1030,7 +1030,7 @@ notice_update_cc_on_set(exp, insn) } else /* if (GET_CODE (SET_DEST (exp)) == MEM) */ { - /* the last else is a bit paranoic, but since nearly all instructions + /* the last else is a bit paranoiac, but since nearly all instructions play with condition codes, it's reasonable! */ CC_STATUS_INIT; /* paranoia*/ diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h index 8cc075b496d..cd2b6da3c8a 100644 --- a/gcc/config/pdp11/pdp11.h +++ b/gcc/config/pdp11/pdp11.h @@ -25,7 +25,7 @@ char *output_move_double(); char *output_move_quad(); char *output_block_move(); -/* check whther load_fpu_reg or not */ +/* check whether load_fpu_reg or not */ #define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11) #define NO_LOAD_FPU_REG_P(x) ((x)==12 || (x)==13) #define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x)) @@ -85,7 +85,7 @@ extern int target_flags; { "abshi", 128}, \ { "no-abshi", -128}, \ /* is branching expensive - on a PDP, it's actually really cheap */ \ -/* this is just to play aroound and check what code gcc generates */ \ +/* this is just to play around and check what code gcc generates */ \ { "branch-expensive", 256}, \ { "branch-cheap", -256}, \ /* optimize for space instead of time - just in a couple of places */ \ @@ -170,7 +170,7 @@ extern int target_flags; /* Define this if most significant word of a multiword number is numbered. */ #define WORDS_BIG_ENDIAN 1 -/* number of bits in an addressible storage unit */ +/* number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. @@ -453,8 +453,8 @@ enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REG operand as its first argument and the constraint letter as its second operand. - `Q' is for memory refereces using take more than 1 instruction. - `R' is for memory refereces which take 1 word for the instruction. */ + `Q' is for memory references using take more than 1 instruction. + `R' is for memory references which take 1 word for the instruction. */ #define EXTRA_CONSTRAINT(OP,CODE) \ ((GET_CODE (OP) != MEM) ? 0 \ diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md index 7f74919b62d..615581015d4 100644 --- a/gcc/config/pdp11/pdp11.md +++ b/gcc/config/pdp11/pdp11.md @@ -63,7 +63,7 @@ ;; length default is 1 word each (define_attr "length" "" (const_int 1)) -;; a users asm staement +;; a user's asm statement (define_asm_attributes [(set_attr "type" "unknown") ; all bets are off how long it is - make it 256, forces long jumps @@ -679,7 +679,7 @@ [(set_attr "length" "8,8,8")]) ;; maybe fiddle a bit with move_ratio, then -;; let contraints only accept a register ... +;; let constraints only accept a register ... (define_expand "movstrhi" [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "=g,g")) @@ -881,7 +881,7 @@ [(set_attr "length" "6")]) ;; make float to int and vice versa -;; using the cc_status.flag field we coulf probably cut down +;; using the cc_status.flag field we could probably cut down ;; on seti and setl ;; assume that we are normally in double and integer mode - ;; what do pdp library routines do to fpu mode ? @@ -1015,7 +1015,7 @@ ;;- subtract instructions ;; we don't have to care for constant second -;; args, since they are cononical plus:xx now! +;; args, since they are canonical plus:xx now! ;; also for minus:DF ?? (define_insn "subdf3" @@ -1058,7 +1058,7 @@ output_asm_insn (\"sub %2, %0\", lateoperands); return \"\"; }" -;; offsetable memory addresses always are expensive!!! +;; offsettable memory addresses always are expensive!!! [(set_attr "length" "3,5,6,8")]) (define_insn "subhi3" diff --git a/gcc/config/rs6000/eabi.asm b/gcc/config/rs6000/eabi.asm index 53a21f3b5c7..a26c730a1a1 100644 --- a/gcc/config/rs6000/eabi.asm +++ b/gcc/config/rs6000/eabi.asm @@ -53,7 +53,7 @@ __eabi: mflr 0 # Normal program, load up register 2 lwz 2,.Lgot(11) # normal GOT address - b __do_global_ctors # do any C++ global contstructors (which returns to caller) + b __do_global_ctors # do any C++ global constructors (which returns to caller) # We need to relocate the .got2 pointers. Don't load register 2 @@ -77,7 +77,7 @@ __eabi: mflr 0 # Done adjusting pointers, return .Ldone: - b __do_global_ctors # do any C++ global contstructors (which returns to caller) + b __do_global_ctors # do any C++ global constructors (which returns to caller) # Routines for saving floating point registers, called by the compiler. # Called with r11 pointing to the stack header word of the caller of the diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 1f06bb6edd2..bbefc031f6b 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1577,7 +1577,7 @@ svr4_traceback (file, name, decl) long alloca_reg; /* stack/frame register */ long fpr_max = 64 - first_fp_reg; /* # of floating point registers saved */ long gpr_max = 32 - first_reg; /* # of general purpose registers saved */ - long sp_max; /* 1 if the function aquires a stack frame */ + long sp_max; /* 1 if the function acquires a stack frame */ long lr_max; /* 1 if the function stores the link register */ long cr_max; /* 1 if the function has a CR save word */ long fpscr_max = 0; /* 1 if the function has a FPSCR save word */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ecbbc3695f4..7e701dbd902 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1453,7 +1453,7 @@ ;; AIX architecture-independent common-mode multiply (DImode), ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and -;; R4; results in R3 and somtimes R4; link register always clobbered by bla +;; R4; results in R3 and sometimes R4; link register always clobbered by bla ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but ;; assumed unused if generating common-mode, so ignore. (define_insn "mulh_call" diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index fd19ef387c1..e31e16ed694 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -417,7 +417,7 @@ do { \ /* The SH has two sorts of general registers, R0 and the rest. R0 can be used as the destination of some of the arithmetic ops. There are also some special purpose registers; the T bit register, the - Procedure Return Register and the Multipy Accumulate Registers. */ + Procedure Return Register and the Multiply Accumulate Registers. */ enum reg_class { @@ -705,7 +705,7 @@ extern int current_function_anonymous_args; /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. - On the SH, the trapoline looks like + On the SH, the trampoline looks like 1 0000 D301 mov.l l1,r3 2 0002 DD02 mov.l l2,r13 3 0004 4D2B jmp @r13 diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index b94f331b2f7..86cdd6b772e 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -297,7 +297,7 @@ ;; we take advantage of the library routines which don't clobber as many ;; registers as a normal function call would. -;; We must use a psuedo-reg forced to reg 0 in the SET_DEST rather than +;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than ;; hard register 0. If we used hard register 0, then the next instruction ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg ;; gets allocated to a stack slot that needs its address reloaded, then diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 4c476efbe37..7a27742028c 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -780,7 +780,7 @@ gen_compare_reg (code, x, y) we need the movcc patterns). It is possible to provide the movcc patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two registers (say %g1,%g5) and it takes about 6 insns. A better fix would be - to tell cse that CCFPE mode registers (even pseudoes) are call + to tell cse that CCFPE mode registers (even pseudos) are call clobbered. */ /* ??? This is an experiment. Rather than making changes to cse which may @@ -1952,7 +1952,7 @@ output_move_quad (operands) abort (); } - /* Normal case: move the four words in lowest to higest address order. */ + /* Normal case: move the four words in lowest to highest address order. */ output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]); @@ -4079,7 +4079,7 @@ sparc_type_code (type) (to store insns). This is a bit excessive. Perhaps a different mechanism would be better here. - Emit 3 FLUSH instructions to synchonize the data and instruction caches. + Emit 3 FLUSH instructions to synchronize the data and instruction caches. ??? v9: We assume the top 32 bits of function addresses are 0. */ @@ -4513,7 +4513,7 @@ sparc_flat_output_function_prologue (file, size) Don't change the order of insns emitted here without checking with the gdb folk first. */ - /* Is the entire register save area offsetable from %sp? */ + /* Is the entire register save area offsettable from %sp? */ if (reg_offset < 4096 - 64 * UNITS_PER_WORD) { if (size <= 4096) @@ -4663,7 +4663,7 @@ sparc_flat_output_function_epilogue (file, size) fp_str, size, sp_str); } - /* Is the entire register save area offsetable from %sp? */ + /* Is the entire register save area offsettable from %sp? */ if (reg_offset < 4096 - 64 * UNITS_PER_WORD) { size1 = 0; diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index c69d400e083..5594f1606f5 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -5243,7 +5243,7 @@ ;; The scan instruction searches from the most significant bit while ffs ;; searches from the least significant bit. The bit index and treatment of ;; zero also differ. It takes at least 7 instructions to get the proper -;; result. Here is an obvious 8 instruction seequence. +;; result. Here is an obvious 8 instruction sequence. (define_insn "ffssi2" [(set (match_operand:SI 0 "register_operand" "=&r") diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md index 6a5c389b4bc..47697319d69 100644 --- a/gcc/config/vax/vax.md +++ b/gcc/config/vax/vax.md @@ -1419,7 +1419,7 @@ ;; When the field position and size are constant and the destination ;; is a register, extv and extzv are much slower than a rotate followed -;; by a bicl or sign extension. Becase we might end up choosing ext[z]v +;; by a bicl or sign extension. Because we might end up choosing ext[z]v ;; anyway, we can't allow immediate values for the primary source operand. (define_insn "" diff --git a/gcc/cp/class.c b/gcc/cp/class.c index 78d0c5d21ee..08c2b5369c3 100644 --- a/gcc/cp/class.c +++ b/gcc/cp/class.c @@ -190,7 +190,7 @@ build_vbase_path (code, type, expr, path, alias_this) (the static type of the complete object), and then convert back to the type we want. Until that is done, or until we can recognize when that is, we cannot do the short cut logic. (mrs) */ - /* Do this, until we can undo any previous convertions. See net35.C + /* Do this, until we can undo any previous conversions. See net35.C for a testcase. */ fixed_type_p = complete_type_p (expr); @@ -2276,7 +2276,7 @@ modify_one_vtable (binfo, t, fndecl, pfn) consideration the virtual base class pointers that we stick in before the virtual function table pointer. - Also, we want just the delta bewteen the most base class + Also, we want just the delta between the most base class that we derived this vfield from and us. */ base_offset = size_binop (PLUS_EXPR, get_derived_offset (binfo, DECL_CONTEXT (current_fndecl)), @@ -2374,7 +2374,7 @@ fixup_vtable_deltas1 (binfo, t) consideration the virtual base class pointers that we stick in before the virtual function table pointer. - Also, we want just the delta bewteen the most base class + Also, we want just the delta between the most base class that we derived this vfield from and us. */ base_offset = size_binop (PLUS_EXPR, get_derived_offset (binfo, DECL_CONTEXT (fndecl)), @@ -2583,7 +2583,7 @@ override_one_vtable (binfo, old, t) return; } { - /* This MUST be overriden, or the class is ill-formed. */ + /* This MUST be overridden, or the class is ill-formed. */ /* For now, we just make it abstract. */ tree fndecl = TREE_OPERAND (FNADDR_FROM_VTABLE_ENTRY (TREE_VALUE (virtuals)), 0); tree vfn; @@ -3722,7 +3722,7 @@ finish_struct (t, list_of_fieldlists, warn_anon) vbases = CLASSTYPE_VBASECLASSES (t); while (vbases) { - /* We might be able to shorten the ammount of work we do by + /* We might be able to shorten the amount of work we do by only doing this for vtables that come from virtual bases that have differing offsets, but don't want to miss any entries. */ @@ -4340,7 +4340,7 @@ pushclass (type, modify) { tree item; - /* Hooray, our cacheing was successful, let's just install the + /* Hooray, we successfully cached; let's just install the cached class_shadowed list, and walk through it to get the IDENTIFIER_TYPE_VALUEs correct. */ set_class_shadows (previous_class_values); diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 828e3f496dd..f2e3c48e64a 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -1464,7 +1464,7 @@ extern tree unknown_type_node; extern tree opaque_type_node, signature_type_node; /* Node for "pointer to (virtual) function". - This may be distinct from ptr_type_node so gdb can distinuish them. */ + This may be distinct from ptr_type_node so gdb can distinguish them. */ #define vfunc_ptr_type_node \ (flag_vtable_thunks ? vtable_entry_type : ptr_type_node) @@ -1783,7 +1783,7 @@ extern int flag_external_templates; extern int flag_alt_external_templates; -/* Nonzero means implicit template instantatiations are emitted. */ +/* Nonzero means implicit template instantiations are emitted. */ extern int flag_implicit_templates; diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index dc78309b806..e695ce23f85 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -430,7 +430,7 @@ extern int flag_huge_objects; /* Nonzero if we want to conserve space in the .o files. We do this by putting uninitialized data and runtime initialized data into - .common instead of .data at the expense of not flaging multiple + .common instead of .data at the expense of not flagging multiple definitions. */ extern int flag_conserve_space; @@ -1223,9 +1223,9 @@ poplevel_class (force) for (shadowed = level->shadowed; shadowed; shadowed = TREE_CHAIN (shadowed)) IDENTIFIER_LOCAL_VALUE (TREE_PURPOSE (shadowed)) = TREE_VALUE (shadowed); /* If we're leaving a toplevel class, don't bother to do the setting - of IDENTIFER_CLASS_VALUE to NULL_TREE, since first of all this slot + of IDENTIFIER_CLASS_VALUE to NULL_TREE, since first of all this slot shouldn't even be used when current_class_type isn't set, and second, - if we don't touch it here, we're able to use the caching effect if the + if we don't touch it here, we're able to use the cache effect if the next time we're entering a class scope, it is the same class. */ if (current_class_depth != 1 || force) for (shadowed = level->class_shadowed; @@ -1729,7 +1729,7 @@ make_type_decl (name, type) #endif /* Push a tag name NAME for struct/class/union/enum type TYPE. - Normally put into into the inner-most non-tag-tranparent scope, + Normally put into into the inner-most non-tag-transparent scope, but if GLOBALIZE is true, put it in the inner-most non-class scope. The latter is needed for implicit declarations. */ @@ -5160,7 +5160,7 @@ init_decl_processing () { flag_inline_functions = 0; #if 0 - /* This causes uneccessary emission of inline functions. */ + /* This causes unnecessary emission of inline functions. */ flag_default_inline = 0; #endif } @@ -11197,7 +11197,7 @@ store_parm_decls () expand_expr (build_function_call (lookup_name (get_identifier ("__gc_main"), 0), NULL_TREE), 0, VOIDmode, 0); #if 0 - /* done at a differnet time */ + /* done at a different time */ if (flag_rtti) output_builtin_tdesc_entries (); #endif diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c index cb326c8a5dd..3d878a60950 100644 --- a/gcc/cp/decl2.c +++ b/gcc/cp/decl2.c @@ -227,7 +227,7 @@ int warn_extern_inline; /* Non-zero means warn when the compiler will reorder code. */ int warn_reorder; -/* Non-zero means warn when sysnthesis behavior differs from Cfront's. */ +/* Non-zero means warn when synthesis behavior differs from Cfront's. */ int warn_synth; /* Nonzero means `$' can be in an identifier. @@ -341,7 +341,7 @@ int flag_huge_objects; /* Nonzero if we want to conserve space in the .o files. We do this by putting uninitialized data and runtime initialized data into - .common instead of .data at the expense of not flaging multiple + .common instead of .data at the expense of not flagging multiple definitions. */ int flag_conserve_space; @@ -985,7 +985,7 @@ grokclassfn (ctype, cname, function, flags, quals) #if 0 /* This code is going into the compiler, but currently, it makes - libg++/src/Interger.cc not compile. The problem is that the nice name + libg++/src/Integer.cc not compile. The problem is that the nice name winds up going into the symbol table, and conversion operations look for the manged name. */ substitute_nice_name (function); @@ -1958,7 +1958,7 @@ build_push_scope (cname, name) return rval; /* We do need to push the scope in this case, since CTYPE helps - determine subsequent intializers (i.e., Foo::Bar x = foo_enum_1;). */ + determine subsequent initializers (i.e., Foo::Bar x = foo_enum_1;). */ push_nested_class (ctype, 3); TREE_COMPLEXITY (rval) = current_class_depth; @@ -3001,7 +3001,7 @@ finish_file () emit_note (input_filename, lineno); /* 9.5p5: The initializer of a static member of a class has - the same acess rights as a member function. */ + the same access rights as a member function. */ DECL_CLASS_CONTEXT (current_function_decl) = DECL_CONTEXT (decl); DECL_STATIC_FUNCTION_P (current_function_decl) = 1; diff --git a/gcc/cp/error.c b/gcc/cp/error.c index d7bbff8d284..26905e2878c 100644 --- a/gcc/cp/error.c +++ b/gcc/cp/error.c @@ -275,7 +275,7 @@ dump_aggr_type (t, v) OB_PUTC2 (':', ':'); } - /* kludge around wierd behavior on g++.brendan/line1.C */ + /* kludge around weird behavior on g++.brendan/line1.C */ if (TREE_CODE (name) != IDENTIFIER_NODE) name = DECL_NAME (name); diff --git a/gcc/cp/except.c b/gcc/cp/except.c index 6c849fcdd5f..78127a1a087 100644 --- a/gcc/cp/except.c +++ b/gcc/cp/except.c @@ -175,7 +175,7 @@ It is a complete rewrite of all the EH stuff that was here before Shortcomings: 1. The type of the throw and catch must still match exactly (no support yet for matching base classes) - 2. Throw specifications of functions still doesnt't work. + 2. Throw specifications of functions still don't work. Cool Things: 1. Destructors are called properly :-) 2. No overhead for the non-exception thrown case. @@ -1282,7 +1282,7 @@ void expand_end_catch_block () /* label for the start of the protection region. */ start_protect_label_rtx = pop_label_entry (&false_label_stack); - /* Cleanup the EH paramater. */ + /* Cleanup the EH parameter. */ decls = getdecls (); expand_end_bindings (decls, decls != NULL_TREE, 0); @@ -1331,7 +1331,7 @@ do_unwind (throw_label) params=tree_cons (NULL_TREE, integer_zero_node, NULL_TREE); fcall = build_function_call (BuiltinReturnAddress, params); return_val_rtx = expand_expr (fcall, NULL_RTX, SImode, 0); - /* In the return, the new pc is pc+8, as the value comming in is + /* In the return, the new pc is pc+8, as the value coming in is really the address of the call insn, not the next insn. */ emit_move_insn (return_val_rtx, plus_constant(gen_rtx (LABEL_REF, Pmode, @@ -1404,9 +1404,9 @@ do_unwind (throw_label) } /* is called from expand_exception_blocks () to generate the code in a function - to "throw" if anything in the function needs to preform a throw. + to "throw" if anything in the function needs to perform a throw. - expands "throw" as the following psuedo code: + expands "throw" as the following pseudo code: throw: eh = find_first_exception_match (saved_pc); diff --git a/gcc/cp/init.c b/gcc/cp/init.c index 39db6447fe3..6b193a36f52 100644 --- a/gcc/cp/init.c +++ b/gcc/cp/init.c @@ -109,7 +109,7 @@ void init_init_processing () pointer to the type of the real derived type that we want to initialize for. This is the case when addr is a pointer to a sub object of a complete object, and we only want to do part of the - complete object's initiailzation of vtable pointers. This is done + complete object's initialization of vtable pointers. This is done for all virtual table pointers in virtual base classes. REAL_BINFO is used to find the BINFO_VTABLE that we initialize with. BINFO is used for conversions of addr to subobjects. @@ -3157,7 +3157,7 @@ build_new (placement, decl, init, use_global_new) /* If we want to check the value of the allocation expression, and the number of elements in the array is not a constant, we *must* expand the SAVE_EXPR for nelts in alloc_expr before we - expand it in the actual initalization. So we need to build up + expand it in the actual initialization. So we need to build up an RTL_EXPR for alloc_expr. Sigh. */ if (alloc_expr && ! TREE_CONSTANT (nelts)) { diff --git a/gcc/cp/lex.c b/gcc/cp/lex.c index 0585787e324..a80b900c18a 100644 --- a/gcc/cp/lex.c +++ b/gcc/cp/lex.c @@ -2544,7 +2544,7 @@ linenum: } } - /* Do the actions implied by the preceeding numbers. */ + /* Do the actions implied by the preceding numbers. */ if (action == act_push) { diff --git a/gcc/cp/search.c b/gcc/cp/search.c index c58683570f2..e14f6ff8950 100644 --- a/gcc/cp/search.c +++ b/gcc/cp/search.c @@ -566,7 +566,7 @@ get_base_distance_recursive (binfo, depth, is_private, basetype_path, rval, Return -3 if PARENT is private to TYPE, and PROTECT is non-zero. If PATH_PTR is non-NULL, then also build the list of types - from PARENT to TYPE, with TREE_VIA_VIRUAL and TREE_VIA_PUBLIC + from PARENT to TYPE, with TREE_VIA_VIRTUAL and TREE_VIA_PUBLIC set. PARENT can also be a binfo, in which case that exact parent is found @@ -2743,7 +2743,7 @@ fixup_virtual_upcast_offsets (real_binfo, binfo, init_self, can_elide, addr, ori are initializing. When USE_COMPUTED_OFFSETS is non-zero, we can assume that the - object was laidout by a top-level contructor and the computed + object was laid out by a top-level constructor and the computed offsets are valid to store vtables. When zero, we must store new vtables through virtual baseclass pointers. diff --git a/gcc/cp/sig.c b/gcc/cp/sig.c index 282dce97717..8378888f7fa 100644 --- a/gcc/cp/sig.c +++ b/gcc/cp/sig.c @@ -239,7 +239,7 @@ build_signature_pointer_or_reference_type (to_type, constp, volatilep, refp) current_obstack = ambient_obstack; saveable_obstack = ambient_saveable_obstack; - /* Ouput debug information for this type. */ + /* Output debug information for this type. */ rest_of_type_compilation (t, 1); return t; diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c index 2927c32af02..280e9dedcc7 100644 --- a/gcc/cp/typeck.c +++ b/gcc/cp/typeck.c @@ -2990,7 +2990,7 @@ build_binary_op_nodefault (code, orig_op0, orig_op1, error_code) resultcode = RDIV_EXPR; else /* When dividing two signed integers, we have to promote to int. - unless we divide by a conatant != -1. Note that default + unless we divide by a constant != -1. Note that default conversion will have been performed on the operands at this point, so we have to dig out the original type to find out if it was unsigned. */ @@ -6171,7 +6171,7 @@ language_lvalue_valid (exp) return 1; } -/* Get differnce in deltas for different pointer to member function +/* Get difference in deltas for different pointer to member function types. Return inetger_zero_node, if FROM cannot be converted to a TO type. If FORCE is true, then allow reverse conversions as well. */ static tree @@ -6253,7 +6253,7 @@ build_ptrmemfunc (type, pfn, force) tree npfn; tree u; - /* Handle multiple conversions of pointer to member fucntions. */ + /* Handle multiple conversions of pointer to member functions. */ if (TYPE_PTRMEMFUNC_P (TREE_TYPE (pfn))) { tree ndelta, ndelta2, nindex; diff --git a/gcc/cp/xref.c b/gcc/cp/xref.c index 283771b1cf7..f1d8ae11709 100644 --- a/gcc/cp/xref.c +++ b/gcc/cp/xref.c @@ -803,7 +803,7 @@ fixname(nam, buf) return buf; } -/* Open file for xrefing. */ +/* Open file for xreffing. */ static void open_xref_file(file) diff --git a/gcc/cplus-dem.c b/gcc/cplus-dem.c index b56e34e2517..30c5eab7dfb 100644 --- a/gcc/cplus-dem.c +++ b/gcc/cplus-dem.c @@ -163,11 +163,11 @@ static const struct optable {"compound", ", ", 0}, /* old */ {"cm", ", ", DMGL_ANSI}, /* ansi */ {"cond", "?:", 0}, /* old */ - {"cn", "?:", DMGL_ANSI}, /* psuedo-ansi */ + {"cn", "?:", DMGL_ANSI}, /* pseudo-ansi */ {"max", ">?", 0}, /* old */ - {"mx", ">?", DMGL_ANSI}, /* psuedo-ansi */ + {"mx", ">?", DMGL_ANSI}, /* pseudo-ansi */ {"min", "<?", 0}, /* old */ - {"mn", "<?", DMGL_ANSI}, /* psuedo-ansi */ + {"mn", "<?", DMGL_ANSI}, /* pseudo-ansi */ {"nop", "", 0}, /* old (for operator=) */ {"rm", "->*", DMGL_ANSI} /* ansi */ }; @@ -955,7 +955,7 @@ demangle_template (work, mangled, tname, trawname) break; default: /* it's probably user defined type, let's assume - it's integeral, it seems hard to figure out + it's integral, it seems hard to figure out what it really is */ done = is_integral = 1; } @@ -2397,10 +2397,9 @@ demangle_args (work, mangled, declp) { /* If we have 10 or more types we might have more than a 1 digit index so we'll have to consume the whole count here. This - will loose if the next thing is a type name preceeded by a + will lose if the next thing is a type name preceded by a count but it's impossible to demangle that case properly anyway. Eg if we already have 12 types is T12Pc "(..., type1, - anyway. Eg if we already have 12 types is T12Pc "(..., type1, Pc, ...)" or "(..., type12, char *, ...)" */ if ((t = consume_count(mangled)) == 0) { diff --git a/gcc/cpplib.c b/gcc/cpplib.c index db60a65cb8f..3f3e2126cba 100644 --- a/gcc/cpplib.c +++ b/gcc/cpplib.c @@ -3111,7 +3111,7 @@ get_directive_token (pfile) This function expects to see "fname" or <fname> on the input. The input is normally in part of the output_buffer following - CPP_WRITTEN, and will get overwriiten by output_line_command. + CPP_WRITTEN, and will get overwritten by output_line_command. I.e. in input file specification has been popped by handle_directive. This is safe. */ @@ -4623,7 +4623,7 @@ cpp_get_token (pfile) if (CPP_BUFFER (pfile)->nominal_fname && next_buf != 0) { /* We're about to return from an #include file. - Emit #line information now (as part of the CPP_POP) restult. + Emit #line information now (as part of the CPP_POP) result. But the #line refers to the file we will pop to. */ cpp_buffer *cur_buffer = CPP_BUFFER (pfile); CPP_BUFFER (pfile) = next_buf; @@ -7441,7 +7441,7 @@ extern const char *const sys_errlist[]; #else extern char *sys_errlist[]; #endif -#else /* HAVE_STERRROR */ +#else /* HAVE_STRERROR */ char *strerror (); #endif #else /* VMS */ diff --git a/gcc/cpplib.h b/gcc/cpplib.h index 861f7757ce9..3036760925a 100644 --- a/gcc/cpplib.h +++ b/gcc/cpplib.h @@ -344,7 +344,7 @@ struct cpp_options { char for_lint; /* Nonzero means handle CHILL comment syntax - and output CHILL string delimeter for __DATE___ etc. */ + and output CHILL string delimiter for __DATE___ etc. */ char chill; |
