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| author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-01-20 06:47:28 +0000 |
|---|---|---|
| committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-01-20 06:47:28 +0000 |
| commit | 279495ada19c0125b42684ebda82d5a514c0cfae (patch) | |
| tree | 78c8580bac2ffbd2c711f0a2f348e76472dc1e0d /gcc/tree-ssa-loop-im.c | |
| parent | 892e7f8c6b5c57bc3b613ce45e9ebc74cbd1c02e (diff) | |
| download | ppe42-gcc-279495ada19c0125b42684ebda82d5a514c0cfae.tar.gz ppe42-gcc-279495ada19c0125b42684ebda82d5a514c0cfae.zip | |
PR target/19511
* config/i386/i386.c (ix86_preferred_reload_class): Return a proper
subclass of the input class.
(ix86_secondary_memory_needed): Always true for cross-MMX classes.
Always true for cross-SSE1 classes. Rationalize conditionals.
* config/i386/i386.h (SSE_CLASS_P, MMX_CLASS_P): Use straight equality.
* config/i386/i386.md (movsi_1): Add MMX/SSE zeros. Fix alternatives
for SSE1. Don't check TARGET_INTER_UNIT_MOVES.
(movdi_2): Add MMX/SSE zeros.
(movdi_1_rex64): Likewise. Don't check TARGET_INTER_UNIT_MOVES.
(movsf_1): Don't check TARGET_INTER_UNIT_MOVES.
(zero_extendsidi2_32, zero_extendsidi2_rex64): Likewise.
(movsi_1_nointernunit, movdi_1_rex64_nointerunit): Remove.
(movsf_1_nointerunit, zero_extendsidi2_32_1): Remove.
(zero_extendsidi2_rex64_1): Remove.
(MOV0 peephole): Check GENERAL_REG_P.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@93948 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/tree-ssa-loop-im.c')
0 files changed, 0 insertions, 0 deletions
