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author | aldyh <aldyh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-06-18 01:35:47 +0000 |
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committer | aldyh <aldyh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-06-18 01:35:47 +0000 |
commit | ead34f59aeb1f6858d28fb5b394ff5419036a99e (patch) | |
tree | 73deecdababef51a80958fcc5dee4038fb6bac71 /gcc/testsuite/gcc.c-torture/execute/simd-1.c | |
parent | 56fb49bf1df77b2b8e4a99ad6af3401c3535ed98 (diff) | |
download | ppe42-gcc-ead34f59aeb1f6858d28fb5b394ff5419036a99e.tar.gz ppe42-gcc-ead34f59aeb1f6858d28fb5b394ff5419036a99e.zip |
2002-06-16 Aldy Hernandez <aldyh@redhat.com>
* gcc.c-torture/execute/simd-1.c: New.
* gcc.dg/simd-1.c: New.
* doc/extend.texi (Vector Extensions): Document that we can
specify simd types not specifically supported by the hardware.
Document that simd types can be used as function arguments.
Document that signness does make a difference in SIMD types.
Misc cleanups and revisions to the "vector extensions" section.
* simplify-rtx.c (simplify_subreg): Simplify subregs of vector
constants.
* expr.c (vector_mode_valid_p): New.
* expr.h: Add vector_mode_valid_p.
* defaults.h (VECTOR_MODE_SUPPORTED_P): Set default.
* emit-rtl.c (immed_double_const): Do not abort on vectors.
* c-common.c (type_for_mode): Always build vector nodes regardless
of VECTOR_MODE_SUPPORTED_P.
(handle_mode_attribute): Error if we can't emulate a nonexisting
vector mode.
(handle_vector_size_attribute): Same.
* optabs.c (expand_binop): Open-code vector operations.
(expand_unop): Open-code vector unops.
(expand_vector_binop): New.
(expand_vector_unop): New.
* c-typeck.c (build_binary_op): Allow vectors in binops.
Allow vectors in conditional operatiors.
(build_unary_op): Allow vectors in unary minus.
* config/rs6000/rs6000.h (ALTIVEC_VECTOR_MODE): Conditionalize on
TARGET_ALTIVEC.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@54727 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite/gcc.c-torture/execute/simd-1.c')
-rw-r--r-- | gcc/testsuite/gcc.c-torture/execute/simd-1.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.c-torture/execute/simd-1.c b/gcc/testsuite/gcc.c-torture/execute/simd-1.c new file mode 100644 index 00000000000..cb503e457d8 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/simd-1.c @@ -0,0 +1,54 @@ +/* Origin: Aldy Hernandez <aldyh@redhat.com> + + Purpose: Test generic SIMD support. This test should work + regardless of if the target has SIMD instructions. +*/ + +typedef int __attribute__((mode(V4SI))) vecint; + +vecint i = { 150, 100, 150, 200 }; +vecint j = { 10, 13, 20, 30 }; +vecint k; + +union { + vecint v; + int i[4]; +} res; + +/* This should go away once we can use == and != on vector types. */ +void +verify (int a1, int a2, int a3, int a4, + int b1, int b2, int b3, int b4) +{ + if (a1 != b1 + || a2 != b2 + || a3 != b3 + || a4 != b4) + abort (); +} + +int +main () +{ + k = i + j; + res.v = k; + + verify (res.i[0], res.i[1], res.i[2], res.i[3], 160, 113, 170, 230); + + k = i * j; + res.v = k; + + verify (res.i[0], res.i[1], res.i[2], res.i[3], 1500, 1300, 3000, 6000); + + k = i / j; + res.v = k; + + verify (res.i[0], res.i[1], res.i[2], res.i[3], 15, 7, 7, 6); + + k = -i; + res.v = k; + verify (res.i[0], res.i[1], res.i[2], res.i[3], + -150, -100, -150, -200); + + exit (0); +} |