2003-06-18 Stephen Clarke <stephen.clarke@superh.com>

            J"orn Rennecke <joern.rennecke@superh.com>

	* bt-load.c: New file.
	* Makefile.in (OBJS): Include bt-load.o
	(bt-load.o): Add dependencies.
	* flags.h (flag_branch_target_load_optimize): Declare.
	(flag_branch_target_load_optimize2): Likewise.
	* hooks.c (hook_reg_class_void_no_regs): New function.
	(hook_bool_bool_false): Likewise.
	* hooks.h (hook_reg_class_void_no_regs, hook_bool_bool_false): Declare.
	* rtl.h (branch_target_load_optimize): Declare.
	* target-def.h (TARGET_BRANCH_TARGET_REGISTER_CLASS): Define.
	(TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED): Likewise.
	(TARGET_INITIALIZER): Include these.
	* target.h (struct gcc_target): Add branch_target_register_class
	and branch_target_register_callee_saved members.
	* toplev.c (enum dump_file_index): Add DFI_branch_target_load
	(dump_file) Add "tars" entry.
	(flag_branch_target_load_optimize): New variable.
	(flag_branch_target_load_optimize2): Likewise.
	(lang_independent_options): Add entries for new options.
	(rest_of_compilation): Call branch_target_load_optimize.
	* doc/tm.texi (TARGET_BRANCH_TARGET_REGISTER_CLASS): Document.
	(TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED): Likewise.
	* doc/invoke.texi: Document -fbranch-target-load-optimize and
	-fbranch-target-load-optimize2.
	* rtl.h (epilogue_completed): Declare.
	* recog.c (epilogue_completed): New variable.
	* toplev.c (rest_of_compilation): Set it.
	* flow.c (mark_regs_live_at_end): Use it.
	* config/ia64/ia64.c (ia64_output_mi_thunk): Set it.
	* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise.
	* config/sh/sh.c (sh_output_mi_thunk): Likewise.
	* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.

	* sh.c (shmedia_space_reserved_for_target_registers): New variable.
	(sh_target_reg_class): New function.
	(sh_optimize_target_register_callee_saved): Likwise.
	(shmedia_target_regs_stack_space): Likewise.
	(shmedia_reserve_space_for_target_registers_p): Likewise.
	(shmedia_target_regs_stack_adjust): Likewise.
	(TARGET_BRANCH_TARGET_REGISTER_CLASS): Override.
	(TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED): Likewise.
	(calc_live_regs): If flag_branch_target_load_optimize2 and
	TARGET_SAVE_ALL_TARGET_REGS is enabled, and we have space reserved
	for target registers, make sure that we save all target registers.
	(sh_expand_prologue, sh_expand_epilogue): Take target register
	optimizations into account.  Collapse stack adjustments if that
	is beneficial.
	(initial_elimination_offset): Reserve space for target registers
	if necessary.
	* sh.h (SAVE_ALL_TR_BIT, TARGET_SAVE_ALL_TARGET_REGS): Define.
	(OPTIMIZATION_OPTIONS): Enable flag_branch_target_load_optimize.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@68165 138bc75d-0d04-0410-961f-82ee72b054a4

2 files changed, 37 insertions, 1 deletions

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a8ea9a7d3cf..5256e66d8ff 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -258,7 +258,8 @@ in the following sections.
 @xref{Optimize Options,,Options that Control Optimization}.
 @gccoptlist{-falign-functions=@var{n}  -falign-jumps=@var{n} @gol
 -falign-labels=@var{n}  -falign-loops=@var{n}  @gol
--fbranch-probabilities  -fcaller-saves  -fcprop-registers @gol
+-fbranch-probabilities  -fbranch-target-load-optimize @gol
+-fbranch-target-load-optimize2 -fcaller-saves  -fcprop-registers @gol
 -fcse-follow-jumps  -fcse-skip-blocks  -fdata-sections @gol
 -fdelayed-branch  -fdelete-null-pointer-checks @gol
 -fexpensive-optimizations  -ffast-math  -ffloat-store @gol
@@ -4420,6 +4421,19 @@ Perform Sparse Conditional Constant Propagation in SSA form.  Requires
 Perform aggressive dead-code elimination in SSA form.  Requires @option{-fssa}.
 Like @option{-fssa}, this is an experimental feature.
 
+@item -fbranch-target-load-optimize
+@opindex fbranch-target-load-optimize
+Perform branch target register load optimization before prologue / epilogue
+threading.
+The use of target registers can typically be exposed only during reload,
+thus hoisting loads out of loops and doing inter-block scheduling needs
+a separate optimization pass.
+
+@item -fbranch-target-load-optimize2
+@opindex fbranch-target-load-optimize2
+Perform branch target register load optimization after prologue / epilogue
+threading.
+
 
 
 
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index b2e767223cc..4ba28b5dccc 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -9271,3 +9271,25 @@ cannot_modify_jumps_past_reload_p ()
 @}
 @end smallexample
 @end deftypefn
+
+@deftypefn {Target Hook} enum reg_class TARGET_BRANCH_TARGET_REGISTER_CLASS (void)
+This target hook returns a register class for which branch target register
+optimizations should be applied.  All registers in this class should be
+usable interchangably.  After reload, registers in this class will be
+re-allocated and loads will be hoisted out of loops and be subjected
+to inter-block scheduling.
+@end deftypefn
+
+@deftypefn {Target Hook} bool TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED (bool @var{after_prologue_epilogue_gen})
+Branch target register optimization will by default exclude callee-saved
+registers
+that are not already live during the current function; if this target hook
+returns true, they will be included.  The target code must than make sure
+that all target registers in the class returned by
+@samp{TARGET_BRANCH_TARGET_REGISTER_CLASS} that might need saving are
+saved.  @var{after_prologue_epilogue_gen} indicates if prologues and
+epilogues have already been generated.  Note, even if you only return
+true when @var{after_prologue_epilogue_gen} is false, you still are likely
+to have to make special provisions in @code{INITIAL_ELIMINATION_OFFSET}
+to reserve space for caller-saved target registers.
+@end deftypefn