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authorvmakarov <vmakarov@138bc75d-0d04-0410-961f-82ee72b054a4>2011-03-28 01:53:24 +0000
committervmakarov <vmakarov@138bc75d-0d04-0410-961f-82ee72b054a4>2011-03-28 01:53:24 +0000
commita5af08d26ce1678e462f91bb3fb9336e30d02ca8 (patch)
tree761665b37aeeeb5eb4e3f9b4770772ea49679cc0 /gcc/config/sh
parent24b0a129a158dc3987a676c625817b9b21e9d4e9 (diff)
downloadppe42-gcc-a5af08d26ce1678e462f91bb3fb9336e30d02ca8.tar.gz
ppe42-gcc-a5af08d26ce1678e462f91bb3fb9336e30d02ca8.zip
2011-03-27 Vladimir Makarov <vmakarov@redhat.com>
PR bootstrap/48307 Revert the previous patch. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@171589 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/sh')
-rw-r--r--gcc/config/sh/sh.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index d45f8c08001..4579af32736 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1133,6 +1133,20 @@ enum reg_class
extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
+/* The following macro defines cover classes for Integrated Register
+ Allocator. Cover classes is a set of non-intersected register
+ classes covering all hard registers used for register allocation
+ purpose. Any move between two registers of a cover class should be
+ cheaper than load or store of the registers. The macro value is
+ array of register classes with LIM_REG_CLASSES used as the end
+ marker. */
+
+#define IRA_COVER_CLASSES \
+{ \
+ GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
+ FPUL_REGS, LIM_REG_CLASSES \
+}
+
/* When this hook returns true for MODE, the compiler allows
registers explicitly used in the rtl to be used as spill registers
but prevents the compiler from extending the lifetime of these
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