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| author | aldyh <aldyh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-03-08 00:30:32 +0000 |
|---|---|---|
| committer | aldyh <aldyh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-03-08 00:30:32 +0000 |
| commit | 56eb76905b1a5a83b8328662265e8f5d58a7c301 (patch) | |
| tree | 846759c89c016d7619b43dd45e046987a21f08fb /gcc/config/rs6000/spe.md | |
| parent | 29aa10adeb7de2207e8ab0140d91bbe2130df9b5 (diff) | |
| download | ppe42-gcc-56eb76905b1a5a83b8328662265e8f5d58a7c301.tar.gz ppe42-gcc-56eb76905b1a5a83b8328662265e8f5d58a7c301.zip | |
* config/rs6000/rs6000-protos.h: Rename output_e500_flip_eq_bit to
output_e500_flip_gt_bit.
* config/rs6000/rs6000.c (print_operand): case D: Print out bit 31
as bit 31.
(rs6000_generate_compare): Fix logic to look at the correct bits.
(output_e500_flip_eq_bit): Rename to output_e500_flip_gt_bit.
Look at GT bit.
(rs6000_emit_sCOND): Rename gen_e500_flip_eq_bit to
gen_e500_flip_gt_bit. Rename gen_move_from_CR_eq_bit to
gen_move_from_CR_gt_bit.
* config/rs6000/rs6000.md ("move_from_CR_eq_bit"): Change bit
("move_from_CR_eq_bit"): Rename to move_from_CR_gt_bit.
(UNSPEC_MV_CR_EQ): Rename to UNSPEC_MV_CR_GT.
* config/rs6000/spe.md ("e500_cr_ior_compare"): New.
(E500_CR_IOR_COMPARE): New constant.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@96063 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/spe.md')
| -rw-r--r-- | gcc/config/rs6000/spe.md | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index b0459829372..79d03ff623f 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -29,6 +29,7 @@ (TSTDFGT_GPR 1009) (CMPDFLT_GPR 1010) (TSTDFLT_GPR 1011) + (E500_CR_IOR_COMPARE 1012) ]) (define_insn "*negsf2_gpr" @@ -2615,14 +2616,14 @@ ;; FP comparison stuff. ;; Flip the GT bit. -(define_insn "e500_flip_eq_bit" +(define_insn "e500_flip_gt_bit" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (unspec:CCFP [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))] "!TARGET_FPRS && TARGET_HARD_FLOAT" "* { - return output_e500_flip_eq_bit (operands[0], operands[1]); + return output_e500_flip_gt_bit (operands[0], operands[1]); }" [(set_attr "type" "cr_logical")]) @@ -2751,3 +2752,13 @@ "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations" "efdtstlt %0,%1,%2" [(set_attr "type" "veccmpsimple")]) + +;; Like cceq_ior_compare, but compare the GT bits. +(define_insn "e500_cr_ior_compare" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y") + (match_operand 2 "cc_reg_operand" "y")] + E500_CR_IOR_COMPARE))] + "TARGET_E500" + "cror 4*%0+gt,4*%1+gt,4*%2+gt" + [(set_attr "type" "cr_logical")]) |
