Merge in gcc2-ss-010999

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@29150 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 206 insertions, 186 deletions

diff --git a/gcc/config/mips/abi64.h b/gcc/config/mips/abi64.h
index ce1e5fe3831..3e4447e5bdd 100644
--- a/gcc/config/mips/abi64.h
+++ b/gcc/config/mips/abi64.h
@@ -134,7 +134,7 @@ extern struct rtx_def *mips_function_value ();
 		ptr = plus_constant (virtual_incoming_args_rtx,		\
 				     - (mips_save_gp_regs		\
 					* UNITS_PER_WORD));		\
-	      mem = gen_rtx (MEM, BLKmode, ptr);			\
+	      mem = gen_rtx_MEM (BLKmode, ptr);			\
 	      /* va_arg is an array access in this case, which causes	\
 		 it to get MEM_IN_STRUCT_P set.  We must set it here	\
 		 so that the insn scheduler won't assume that these	\
@@ -167,15 +167,15 @@ extern struct rtx_def *mips_function_value ();
 	      for (i = 0; i < mips_save_fp_regs; i++)			\
 		{							\
 		  rtx tem =						\
-		    gen_rtx (MEM, mode,					\
-			     plus_constant (virtual_incoming_args_rtx,	\
-					    off));			\
+		    gen_rtx_MEM (mode,					\
+				 plus_constant (virtual_incoming_args_rtx, \
+						off));			\
 		  emit_move_insn (tem,					\
-				  gen_rtx (REG, mode,			\
-					   ((CUM).fp_arg_words		\
-					    + FP_ARG_FIRST		\
-					    + i				\
-					    + mips_fp_off)));		\
+				  gen_rtx_REG (mode,			\
+					       ((CUM).fp_arg_words	\
+						+ FP_ARG_FIRST		\
+						+ i			\
+						+ mips_fp_off)));	\
 		  off += size;						\
 		  if (! TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)		\
 		    ++i;						\
@@ -193,8 +193,7 @@ extern struct rtx_def *mips_function_value ();
    argument itself.  The pointer is passed in whatever way is appropriate
    for passing a pointer to that type.  */
 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
-  (mips_abi == ABI_EABI							\
-   && function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED))
+  function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
 
 /* A C expression that indicates when it is the called function's
    responsibility to make a copy of arguments passed by invisible
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index a090a2e758e..e65e4be7a8d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -29,7 +29,6 @@ Boston, MA 02111-1307, USA.  */
 #include "config.h"
 #include "system.h"
 #include <signal.h>
-
 #include "rtl.h"
 #include "regs.h"
 #include "hard-reg-set.h"
@@ -41,6 +40,8 @@ Boston, MA 02111-1307, USA.  */
 #include "insn-codes.h"
 #include "recog.h"
 #include "toplev.h"
+#include "output.h"
+
 #include "tree.h"
 #include "function.h"
 #include "expr.h"
@@ -1478,14 +1479,14 @@ mips_fill_delay_slot (ret, type, operands, cur_insn)
   mips_load_reg = set_reg;
   if (GET_MODE_SIZE (mode)
       > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
-    mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
+    mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
   else
     mips_load_reg2 = 0;
 
   if (type == DELAY_HILO)
     {
-      mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
-      mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
+      mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
+      mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
     }
   else
     {
@@ -1646,9 +1647,10 @@ embedded_pic_offset (x)
       pop_topmost_sequence ();
     }
 
-  return gen_rtx (CONST, Pmode,
-		  gen_rtx (MINUS, Pmode, x,
-			   XEXP (DECL_RTL (current_function_decl), 0)));
+  return
+    gen_rtx_CONST (Pmode,
+		   gen_rtx_MINUS (Pmode, x,
+				  XEXP (DECL_RTL (current_function_decl), 0)));
 }
 
 /* Return the appropriate instructions to move one operand to another.  */
@@ -2790,7 +2792,7 @@ gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
   else if (test == ITEST_EQ)
     {
       reg2 = invert ? gen_reg_rtx (mode) : result;
-      convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
+      convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
       reg = reg2;
     }
 
@@ -2857,7 +2859,7 @@ gen_conditional_branch (operands, test_code)
     case CMP_SF:
     case CMP_DF:
       if (mips_isa < 4)
-	reg = gen_rtx (REG, CCmode, FPSW_REGNUM);
+	reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
       else
 	reg = gen_reg_rtx (CCmode);
 
@@ -2865,10 +2867,10 @@ gen_conditional_branch (operands, test_code)
          0 in the instruction built below.  The MIPS FPU handles
          inequality testing by testing for equality and looking for a
          false result.  */
-      emit_insn (gen_rtx (SET, VOIDmode, reg,
-			  gen_rtx (test_code == NE ? EQ : test_code,
-				   CCmode, cmp0, cmp1)));
-
+      emit_insn (gen_rtx_SET (VOIDmode, reg,
+			      gen_rtx (test_code == NE ? EQ : test_code,
+				       CCmode, cmp0, cmp1)));
+      
       test_code = test_code == NE ? EQ : NE;
       mode = CCmode;
       cmp0 = reg;
@@ -2882,7 +2884,7 @@ gen_conditional_branch (operands, test_code)
 
   /* Generate the branch.  */
 
-  label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
+  label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
   label2 = pc_rtx;
 
   if (invert)
@@ -2891,10 +2893,11 @@ gen_conditional_branch (operands, test_code)
       label1 = pc_rtx;
     }
 
-  emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			   gen_rtx (IF_THEN_ELSE, VOIDmode,
-				    gen_rtx (test_code, mode, cmp0, cmp1),
-				    label1, label2)));
+  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+			       gen_rtx_IF_THEN_ELSE (VOIDmode,
+						     gen_rtx (test_code, mode,
+							      cmp0, cmp1),
+						     label1, label2)));
 }
 
 /* Emit the common code for conditional moves.  OPERANDS is the array
@@ -2973,14 +2976,15 @@ gen_conditional_move (operands)
     abort ();
 
   cmp_reg = gen_reg_rtx (cmp_mode);
-  emit_insn (gen_rtx (SET, cmp_mode, cmp_reg,
-		      gen_rtx (cmp_code, cmp_mode, op0, op1)));
-
-  emit_insn (gen_rtx (SET, op_mode, operands[0],
-		      gen_rtx (IF_THEN_ELSE, op_mode,
-			       gen_rtx (move_code, VOIDmode,
-					cmp_reg, CONST0_RTX (SImode)),
-			       operands[2], operands[3])));
+  emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
+			  gen_rtx (cmp_code, cmp_mode, op0, op1)));
+
+  emit_insn (gen_rtx_SET (op_mode, operands[0],
+			  gen_rtx_IF_THEN_ELSE (op_mode,
+						gen_rtx (move_code, VOIDmode,
+							 cmp_reg,
+							 CONST0_RTX (SImode)),
+						operands[2], operands[3])));
 }
 
 /* Write a loop to move a constant number of bytes.
@@ -3097,13 +3101,13 @@ block_move_call (dest_reg, src_reg, bytes_rtx)
     bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
 
 #ifdef TARGET_MEM_FUNCTIONS
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
+  emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
 		     VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
 		     convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
 				      TREE_UNSIGNED (sizetype)),
 		     TYPE_MODE (sizetype));
 #else
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
+  emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
 		     VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
 		     convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
 				      TREE_UNSIGNED (integer_type_node)),
@@ -3502,23 +3506,23 @@ output_block_move (insn, operands, num_regs, move_type)
 		    abort ();
 
 		  if (GET_MODE (operands[i + 4]) != load_store[i].mode)
-		    operands[i + 4] = gen_rtx (REG, load_store[i].mode,
-					       REGNO (operands[i + 4]));
+		    operands[i + 4] = gen_rtx_REG (load_store[i].mode,
+						   REGNO (operands[i + 4]));
 
 		  offset = load_store[i].offset;
 		  xoperands[0] = operands[i + 4];
-		  xoperands[1] = gen_rtx (MEM, load_store[i].mode,
-					  plus_constant (src_reg, offset));
+		  xoperands[1] = gen_rtx_MEM (load_store[i].mode,
+					      plus_constant (src_reg, offset));
 
 		  if (use_lwl_lwr)
 		    {
 		      int extra_offset
 			= GET_MODE_SIZE (load_store[i].mode) - 1;
 
-		      xoperands[2] = gen_rtx (MEM, load_store[i].mode,
-					      plus_constant (src_reg,
-							     extra_offset
-							     + offset));
+		      xoperands[2] = gen_rtx_MEM (load_store[i].mode,
+						  plus_constant (src_reg,
+								 extra_offset
+								 + offset));
 		    }
 
 		  output_asm_insn (load_store[i].load, xoperands);
@@ -3531,17 +3535,17 @@ output_block_move (insn, operands, num_regs, move_type)
 	      int offset = load_store[i].offset;
 
 	      xoperands[0] = operands[i + 4];
-	      xoperands[1] = gen_rtx (MEM, load_store[i].mode,
-				      plus_constant (dest_reg, offset));
+	      xoperands[1] = gen_rtx_MEM (load_store[i].mode,
+					  plus_constant (dest_reg, offset));
 
 
 	      if (use_lwl_lwr)
 		{
 		  int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
-		  xoperands[2] = gen_rtx (MEM, load_store[i].mode,
-					  plus_constant (dest_reg,
-							 extra_offset
-							 + offset));
+		  xoperands[2] = gen_rtx_MEM (load_store[i].mode,
+					      plus_constant (dest_reg,
+							     extra_offset
+							     + offset));
 		}
 
 	      if (move_type == BLOCK_MOVE_NORMAL)
@@ -3814,7 +3818,7 @@ function_arg (cum, mode, type, named)
 
       if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
 	  || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named)
-	ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
+	ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
       else
 	{
 	  /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
@@ -3834,7 +3838,7 @@ function_arg (cum, mode, type, named)
 	  /* If the whole struct fits a DFmode register,
 	     we don't need the PARALLEL.  */
 	  if (! field || mode == DFmode)
-	    ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
+	    ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
 	  else
 	    {
 	      /* Now handle the special case by returning a PARALLEL
@@ -3853,7 +3857,7 @@ function_arg (cum, mode, type, named)
 
 	      /* assign_parms checks the mode of ENTRY_PARM, so we must
 		 use the actual mode here.  */
-	      ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks));
+	      ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
 
 	      bitpos = 0;
 	      regno = regbase + *arg_words + bias;
@@ -3872,14 +3876,14 @@ function_arg (cum, mode, type, named)
 		      && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
 		      && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
 		      && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
-		    reg = gen_rtx (REG, DFmode,
-				   regno + FP_ARG_FIRST - GP_ARG_FIRST);
+		    reg = gen_rtx_REG (DFmode,
+				       regno + FP_ARG_FIRST - GP_ARG_FIRST);
 		  else
-		    reg = gen_rtx (REG, word_mode, regno);
-
+		    reg = gen_rtx_REG (word_mode, regno);
+		  
 		  XVECEXP (ret, 0, i) 
-		    = gen_rtx (EXPR_LIST, VOIDmode, reg,
-			       GEN_INT (bitpos / BITS_PER_UNIT));
+		    = gen_rtx_EXPR_LIST (VOIDmode, reg,
+					 GEN_INT (bitpos / BITS_PER_UNIT));
 
 		  bitpos += 64;
 		  regno++;
@@ -3915,7 +3919,7 @@ function_arg (cum, mode, type, named)
 	{
 	  rtx amount = GEN_INT (BITS_PER_WORD
 				- int_size_in_bytes (type) * BITS_PER_UNIT);
-	  rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias);
+	  rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
 
 	  if (TARGET_64BIT)
 	    cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
@@ -5773,7 +5777,7 @@ save_restore_insns (store_p, large_reg, large_offset, file)
 	       && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
 	       && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
 	{
-	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
+	  base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
 	  base_offset = large_offset;
 	  if (file == 0)
 	    {
@@ -5796,7 +5800,7 @@ save_restore_insns (store_p, large_reg, large_offset, file)
 
       else
 	{
-	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
+	  base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
 	  base_offset = gp_offset;
 	  if (file == 0)
 	    {
@@ -5990,7 +5994,7 @@ save_restore_insns (store_p, large_reg, large_offset, file)
 	       && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
 	       && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
 	{
-	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
+	  base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
 	  base_offset = large_offset;
 	  if (file == 0)
 	    {
@@ -6014,7 +6018,7 @@ save_restore_insns (store_p, large_reg, large_offset, file)
 
       else
 	{
-	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
+	  base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
 	  base_offset = fp_offset;
 	  if (file == 0)
 	    {
@@ -6665,7 +6669,7 @@ mips_expand_prologue ()
 
       if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
 	emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
-			       gen_rtx (REG, DImode, 25)));
+			       gen_rtx_REG (DImode, 25)));
     }
 
   /* If we are profiling, make sure no instructions are scheduled before
@@ -6794,7 +6798,7 @@ mips_expand_epilogue ()
 
   if (tsize > 32767 && ! TARGET_MIPS16)
     {
-      tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
+      tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
       emit_move_insn (tmp_rtx, tsize_rtx);
       tsize_rtx = tmp_rtx;
     }
@@ -7111,12 +7115,13 @@ mips_function_value (valtype, func)
 		 strictly necessary.  */
 	      enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
 
-	      return gen_rtx (PARALLEL, mode,
-			      gen_rtvec (1,
-					 gen_rtx (EXPR_LIST, VOIDmode,
-						  gen_rtx (REG, field_mode,
-							   FP_RETURN),
-						  const0_rtx)));
+	      return gen_rtx_PARALLEL
+		(mode,
+		 gen_rtvec (1,
+			    gen_rtx_EXPR_LIST (VOIDmode,
+					       gen_rtx_REG (field_mode,
+							    FP_RETURN),
+					       const0_rtx)));
 	    }
 
 	  else if (i == 2)
@@ -7130,23 +7135,24 @@ mips_function_value (valtype, func)
 	      int second_offset
 		= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
 
-	      return gen_rtx (PARALLEL, mode,
-			      gen_rtvec (2,
-					 gen_rtx (EXPR_LIST, VOIDmode,
-						  gen_rtx (REG, first_mode,
-							   FP_RETURN),
-						  GEN_INT (first_offset
-							   / BITS_PER_UNIT)),
-					 gen_rtx (EXPR_LIST, VOIDmode,
-						  gen_rtx (REG, second_mode,
-							   FP_RETURN + 2),
-						  GEN_INT (second_offset
-							   / BITS_PER_UNIT))));
+	      return gen_rtx_PARALLEL
+		(mode,
+		 gen_rtvec (2,
+			    gen_rtx_EXPR_LIST (VOIDmode,
+					       gen_rtx_REG (first_mode,
+							    FP_RETURN),
+					       GEN_INT (first_offset
+							/ BITS_PER_UNIT)),
+			    gen_rtx_EXPR_LIST (VOIDmode,
+					       gen_rtx_REG (second_mode,
+							    FP_RETURN + 2),
+					       GEN_INT (second_offset
+							/ BITS_PER_UNIT))));
 	    }
 	}
     }
 
-  return gen_rtx (REG, mode, reg);
+  return gen_rtx_REG (mode, reg);
 }
 
 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE.  Return
@@ -7161,6 +7167,18 @@ function_arg_pass_by_reference (cum, mode, type, named)
 {
   int size;
 
+  /* We must pass by reference if we would be both passing in registers
+     and the stack.  This is because any subsequent partial arg would be
+     handled incorrectly in this case.
+
+     ??? This is really a kludge.  We should either fix GCC so that such
+     a situation causes an abort and then do something in the MIPS port
+     to prevent it, or add code to function.c to properly handle the case.  */
+  if (FUNCTION_ARG (*cum, mode, type, named) != 0
+      && MUST_PASS_IN_STACK (mode, type))
+    return 1;
+
+  /* Otherwise, we only do this if EABI is selected.  */
   if (mips_abi != ABI_EABI)
     return 0;
 
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index e80eb6afeb9..084f5d2a925 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1131,7 +1131,7 @@ while (0)
 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
 
 /* Before the prologue, RA lives in r31.  */
-#define INCOMING_RETURN_ADDR_RTX  gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
+#define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
 
 /* Overrides for the COFF debug format.  */
 #define PUT_SDB_SCL(a)					\
@@ -2164,7 +2164,7 @@ extern enum reg_class	mips_secondary_reload_class ();
 
 #define RETURN_ADDR_RTX(count, frame)			\
   ((count == 0)						\
-   ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
+   ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
    : (rtx) 0)
 
 /* Structure to be filled in by compute_frame_size with register
@@ -2706,19 +2706,19 @@ typedef struct mips_args {
   rtx addr = ADDR;							    \
   if (Pmode == DImode)							    \
     {									    \
-      emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
-      emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
+      emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
+      emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
     }									    \
   else									    \
     {									    \
-      emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
-      emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
+      emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
+      emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
     }									    \
 									    \
   /* Flush both caches.  We need to flush the data cache in case	    \
      the system has a write-back cache.  */				    \
   /* ??? Should check the return value for errors.  */			    \
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC),	    \
+  emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC),	    \
 		     0, VOIDmode, 3, addr, Pmode,			    \
 		     GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
 		     GEN_INT (3), TYPE_MODE (integer_type_node));	    \
@@ -3050,8 +3050,10 @@ typedef struct mips_args {
   if (mips_split_addresses && mips_check_split (X, MODE))		\
     {									\
       /* ??? Is this ever executed?  */					\
-      X = gen_rtx (LO_SUM, Pmode,					\
-		   copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
+      X = gen_rtx_LO_SUM (Pmode,					\
+			  copy_to_mode_reg (Pmode,			\
+					    gen_rtx (HIGH, Pmode, X)),	\
+			  X);						\
       goto WIN;								\
     }									\
 									\
@@ -3067,7 +3069,7 @@ typedef struct mips_args {
 									\
       emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0));		\
 									\
-      X = gen_rtx (PLUS, Pmode, ptr_reg, constant);			\
+      X = gen_rtx_PLUS (Pmode, ptr_reg, constant);			\
       if (SMALL_INT (constant))						\
 	goto WIN;							\
       /* Otherwise we fall through so the code below will fix the	\
@@ -3099,12 +3101,12 @@ typedef struct mips_args {
 	  emit_move_insn (int_reg,					\
 			  GEN_INT (INTVAL (xplus1) & ~ 0x7fff));	\
 									\
-	  emit_insn (gen_rtx (SET, VOIDmode,				\
-			      ptr_reg,					\
-			      gen_rtx (PLUS, Pmode, xplus0, int_reg)));	\
+	  emit_insn (gen_rtx_SET (VOIDmode,				\
+				  ptr_reg,				\
+				  gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
 									\
-	  X = gen_rtx (PLUS, Pmode, ptr_reg,				\
-		       GEN_INT (INTVAL (xplus1) & 0x7fff));		\
+	  X = gen_rtx_PLUS (Pmode, ptr_reg,				\
+			    GEN_INT (INTVAL (xplus1) & 0x7fff));	\
 	  goto WIN;							\
 	}								\
     }									\
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 7b860edc652..ff03d01e1d5 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1,9 +1,9 @@
 ;;  Mips.md	     Machine Description for MIPS based processors
+;;  Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
 ;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr
 ;;  Changes by       Michael Meissner, meissner@osf.org
 ;;  64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
 ;;  Brendan Eich, brendan@microunity.com.
-;;  Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
 
 ;; This file is part of GNU CC.
 
@@ -1701,7 +1701,7 @@
   rtx xoperands[10];
 
   xoperands[0] = operands[0];
-  xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM);
+  xoperands[1] = gen_rtx_REG (SImode, LO_REGNUM);
 
   output_asm_insn (\"mult\\t%1,%2\", operands);
   output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
@@ -1829,13 +1829,13 @@
     output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
   else 
     {
-    rtx xoperands[10];
+      rtx xoperands[10];
 
-    xoperands[0] = operands[0];
-    xoperands[1] = gen_rtx (REG, DImode, LO_REGNUM);
+      xoperands[0] = operands[0];
+      xoperands[1] = gen_rtx_REG (DImode, LO_REGNUM);
 
-    output_asm_insn (\"dmult\\t%1,%2\", operands);
-    output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
+      output_asm_insn (\"dmult\\t%1,%2\", operands);
+      output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
     }
   return \"\";
 }"
@@ -4265,12 +4265,12 @@ move\\t%0,%z4\\n\\
       emit_jump_insn (gen_bge (label1));
 
       emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			       gen_rtx (LABEL_REF, VOIDmode, label2)));
+      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+				   gen_rtx_LABEL_REF (VOIDmode, label2)));
       emit_barrier ();
 
       emit_label (label1);
-      emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
+      emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
       emit_move_insn (reg3, GEN_INT (0x80000000));
 
       emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
@@ -4280,7 +4280,7 @@ move\\t%0,%z4\\n\\
 
       /* allow REG_NOTES to be set on last insn (labels don't have enough
 	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
+      emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
       DONE;
     }
 }")
@@ -4308,12 +4308,12 @@ move\\t%0,%z4\\n\\
       emit_jump_insn (gen_bge (label1));
 
       emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			       gen_rtx (LABEL_REF, VOIDmode, label2)));
+      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+				   gen_rtx_LABEL_REF (VOIDmode, label2)));
       emit_barrier ();
 
       emit_label (label1);
-      emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
+      emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
       emit_move_insn (reg3, GEN_INT (0x80000000));
       emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
 
@@ -4324,7 +4324,7 @@ move\\t%0,%z4\\n\\
 
       /* allow REG_NOTES to be set on last insn (labels don't have enough
 	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
+      emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
       DONE;
     }
 }")
@@ -4352,12 +4352,12 @@ move\\t%0,%z4\\n\\
       emit_jump_insn (gen_bge (label1));
 
       emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			       gen_rtx (LABEL_REF, VOIDmode, label2)));
+      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+				   gen_rtx_LABEL_REF (VOIDmode, label2)));
       emit_barrier ();
 
       emit_label (label1);
-      emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
+      emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
       emit_move_insn (reg3, GEN_INT (0x80000000));
 
       emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
@@ -4367,7 +4367,7 @@ move\\t%0,%z4\\n\\
 
       /* allow REG_NOTES to be set on last insn (labels don't have enough
 	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
+      emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
       DONE;
     }
 }")
@@ -4395,12 +4395,12 @@ move\\t%0,%z4\\n\\
       emit_jump_insn (gen_bge (label1));
 
       emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			       gen_rtx (LABEL_REF, VOIDmode, label2)));
+      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+				   gen_rtx_LABEL_REF (VOIDmode, label2)));
       emit_barrier ();
 
       emit_label (label1);
-      emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
+      emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
       emit_move_insn (reg3, GEN_INT (0x80000000));
       emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
 
@@ -4411,7 +4411,7 @@ move\\t%0,%z4\\n\\
 
       /* allow REG_NOTES to be set on last insn (labels don't have enough
 	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
+      emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
       DONE;
     }
 }")
@@ -4729,10 +4729,10 @@ move\\t%0,%z4\\n\\
       rtx tem = ((reload_in_progress | reload_completed)
 		 ? operands[0] : gen_reg_rtx (mode));
 
-      emit_insn (gen_rtx (SET, VOIDmode, tem,
-			  gen_rtx (HIGH, mode, operands[1])));
+      emit_insn (gen_rtx_SET (VOIDmode, tem,
+			      gen_rtx_HIGH (mode, operands[1])));
 
-      operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]);
+      operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
     }
 
   /* If we are generating embedded PIC code, and we are referring to a
@@ -4746,8 +4746,8 @@ move\\t%0,%z4\\n\\
       rtx temp;
 
       temp = embedded_pic_offset (operands[1]);
-      temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
-		      force_reg (DImode, temp));
+      temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_rtx,
+			   force_reg (DImode, temp));
       emit_move_insn (operands[0], force_reg (DImode, temp));
       DONE;
     }
@@ -4762,7 +4762,7 @@ move\\t%0,%z4\\n\\
       if (! SMALL_INT (temp2))
 	temp2 = force_reg (DImode, temp2);
 
-      emit_move_insn (operands[0], gen_rtx (PLUS, DImode, temp, temp2));
+      emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
       DONE;
     }
 
@@ -4972,10 +4972,10 @@ move\\t%0,%z4\\n\\
   "TARGET_64BIT"
   "
 {
-  rtx scratch = gen_rtx (REG, DImode,
-			 (REGNO (operands[0]) == REGNO (operands[2]) 
-			  ? REGNO (operands[2]) + 1
-			  : REGNO (operands[2])));
+  rtx scratch = gen_rtx_REG (DImode,
+			     (REGNO (operands[0]) == REGNO (operands[2]) 
+			      ? REGNO (operands[2]) + 1
+			      : REGNO (operands[2])));
 
   if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
     {
@@ -4985,7 +4985,7 @@ move\\t%0,%z4\\n\\
 	  rtx addr = find_replacement (&XEXP (operands[1], 0));
 	  rtx op1 = change_address (operands[1], VOIDmode, addr);
 
-	  scratch = gen_rtx (REG, SImode, REGNO (scratch));
+	  scratch = gen_rtx_REG (SImode, REGNO (scratch));
 	  memword = change_address (op1, SImode, NULL_RTX);
 	  offword = change_address (adj_offsettable_operand (op1, 4),
 				    SImode, NULL_RTX);
@@ -5000,7 +5000,7 @@ move\\t%0,%z4\\n\\
 	      loword = memword;
 	    }
 	  emit_move_insn (scratch, hiword);
-	  emit_move_insn (gen_rtx (REG, SImode, 64), scratch);
+	  emit_move_insn (gen_rtx_REG (SImode, 64), scratch);
 	  emit_move_insn (scratch, loword);
 	  emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
           emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
@@ -5008,7 +5008,7 @@ move\\t%0,%z4\\n\\
       else
 	{
 	  emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
-	  emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
+	  emit_insn (gen_movdi (gen_rtx_REG (DImode, 64), scratch));
 	  emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
 	  emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
 	  emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
@@ -5018,10 +5018,10 @@ move\\t%0,%z4\\n\\
     }
   if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
     {
-      emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
+      emit_insn (gen_movdi (scratch, gen_rtx_REG (DImode, 65)));
       emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
       emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
-      emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
+      emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 64)));
       emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
       emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
       emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
@@ -5065,7 +5065,7 @@ move\\t%0,%z4\\n\\
 	  rtx addr = find_replacement (&XEXP (operands[0], 0));
 	  rtx op0 = change_address (operands[0], VOIDmode, addr);
 
-	  scratch = gen_rtx (REG, SImode, REGNO (operands[2]));
+	  scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
 	  memword = change_address (op0, SImode, NULL_RTX);
 	  offword = change_address (adj_offsettable_operand (op0, 4),
 				    SImode, NULL_RTX);
@@ -5079,9 +5079,9 @@ move\\t%0,%z4\\n\\
 	      hiword = offword;
 	      loword = memword;
 	    }
-	  emit_move_insn (scratch, gen_rtx (REG, SImode, 64));
+	  emit_move_insn (scratch, gen_rtx_REG (SImode, 64));
 	  emit_move_insn (hiword, scratch);
-	  emit_move_insn (scratch, gen_rtx (REG, SImode, 65));
+	  emit_move_insn (scratch, gen_rtx_REG (SImode, 65));
 	  emit_move_insn (loword, scratch);
 	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
 	}
@@ -5151,10 +5151,10 @@ move\\t%0,%z4\\n\\
       rtx tem = ((reload_in_progress | reload_completed)
 		 ? operands[0] : gen_reg_rtx (mode));
 
-      emit_insn (gen_rtx (SET, VOIDmode, tem,
-			  gen_rtx (HIGH, mode, operands[1])));
+      emit_insn (gen_rtx_SET (VOIDmode, tem,
+			      gen_rtx_HIGH (mode, operands[1])));
 
-      operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]);
+      operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
     }
 
   /* If we are generating embedded PIC code, and we are referring to a
@@ -5168,8 +5168,8 @@ move\\t%0,%z4\\n\\
       rtx temp;
 
       temp = embedded_pic_offset (operands[1]);
-      temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
-		      force_reg (SImode, temp));
+      temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_rtx,
+			   force_reg (SImode, temp));
       emit_move_insn (operands[0], force_reg (SImode, temp));
       DONE;
     }
@@ -5184,7 +5184,7 @@ move\\t%0,%z4\\n\\
       if (! SMALL_INT (temp2))
 	temp2 = force_reg (SImode, temp2);
 
-      emit_move_insn (operands[0], gen_rtx (PLUS, SImode, temp, temp2));
+      emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, temp2));
       DONE;
     }
 
@@ -5429,7 +5429,7 @@ move\\t%0,%z4\\n\\
   if (TARGET_64BIT
       && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
     {
-      emit_insn (gen_movsi (gen_rtx (REG, SImode, 65), operands[1]));
+      emit_insn (gen_movsi (gen_rtx_REG (SImode, 65), operands[1]));
       emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
       emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
       emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
@@ -5596,17 +5596,17 @@ move\\t%0,%z4\\n\\
   if (GET_CODE (operands[1]) == MEM)
     source = change_address (operands[1], SFmode, NULL_RTX);
   else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
-    source = gen_rtx (REG, SFmode, true_regnum (operands[1]));
+    source = gen_rtx_REG (SFmode, true_regnum (operands[1]));
   else
     source = operands[1];
 
-  fp1 = gen_rtx (REG, SFmode, REGNO (operands[2]));
-  fp2 = gen_rtx (REG, SFmode, REGNO (operands[2]) + 1);
+  fp1 = gen_rtx_REG (SFmode, REGNO (operands[2]));
+  fp2 = gen_rtx_REG (SFmode, REGNO (operands[2]) + 1);
 
   emit_insn (gen_move_insn (fp1, source));
-  emit_insn (gen_move_insn (fp2, gen_rtx (REG, SFmode, 0)));
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-		      gen_rtx (LT, CCmode, fp2, fp1)));
+  emit_insn (gen_move_insn (fp2, gen_rtx_REG (SFmode, 0)));
+  emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+			  gen_rtx_LT (CCmode, fp2, fp1)));
 
   DONE;
 }")
@@ -5692,7 +5692,7 @@ move\\t%0,%z4\\n\\
 (define_insn ""
   [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "register_operand" "d")))
-	(match_operand:SF 0 "register_operand" "=f"))]
+	(match_operand:SF 0 "register_operand" "f"))]
   "mips_isa >= 4 && TARGET_HARD_FLOAT"
   "swxc1\\t%0,%1(%2)"
   [(set_attr "type"	"store")
@@ -5701,7 +5701,7 @@ move\\t%0,%z4\\n\\
 (define_insn ""
   [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
 			 (match_operand:DI 2 "se_register_operand" "d")))
-	(match_operand:SF 0 "register_operand" "=f"))]
+	(match_operand:SF 0 "register_operand" "f"))]
   "mips_isa >= 4 && TARGET_HARD_FLOAT"
   "swxc1\\t%0,%1(%2)"
   [(set_attr "type"	"store")
@@ -5710,7 +5710,7 @@ move\\t%0,%z4\\n\\
 (define_insn ""
   [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "register_operand" "d")))
-	(match_operand:DF 0 "register_operand" "=f"))]
+	(match_operand:DF 0 "register_operand" "f"))]
   "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
   "sdxc1\\t%0,%1(%2)"
   [(set_attr "type"	"store")
@@ -5719,7 +5719,7 @@ move\\t%0,%z4\\n\\
 (define_insn ""
   [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
 			 (match_operand:DI 2 "se_register_operand" "d")))
-	(match_operand:DF 0 "register_operand" "=f"))]
+	(match_operand:DF 0 "register_operand" "f"))]
   "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
   "sdxc1\\t%0,%1(%2)"
   [(set_attr "type"	"store")
@@ -6551,9 +6551,9 @@ move\\t%0,%z4\\n\\
 {
   int amount = INTVAL (operands[2]);
 
-  operands[2] = GEN_INT ((amount & 31));
+  operands[2] = GEN_INT (amount & 31);
   operands[4] = const0_rtx;
-  operands[5] = GEN_INT (((-amount) & 31));
+  operands[5] = GEN_INT ((-amount) & 31);
 
   return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
 }"
@@ -6592,8 +6592,8 @@ move\\t%0,%z4\\n\\
   "
 {
   int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
 }")
 
 
@@ -6627,8 +6627,8 @@ move\\t%0,%z4\\n\\
   "
 {
   int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
 }")
 
 
@@ -6905,8 +6905,8 @@ move\\t%0,%z4\\n\\
 {
   int amount = INTVAL (operands[2]);
 
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
 
   return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
 }"
@@ -6945,8 +6945,8 @@ move\\t%0,%z4\\n\\
   "
 {
   int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
 }")
 
 
@@ -6980,8 +6980,8 @@ move\\t%0,%z4\\n\\
   "
 {
   int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
 }")
 
 
@@ -7290,8 +7290,8 @@ move\\t%0,%z4\\n\\
 {
   int amount = INTVAL (operands[2]);
 
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
 
   return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
 }"
@@ -7330,8 +7330,8 @@ move\\t%0,%z4\\n\\
   "
 {
   int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
 }")
 
 
@@ -7365,8 +7365,8 @@ move\\t%0,%z4\\n\\
   "
 {
   int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
+  operands[2] = GEN_INT (amount & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
 }")
 
 
@@ -8775,7 +8775,7 @@ move\\t%0,%z4\\n\\
   "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
   "*
 {
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
   return \"sltu\\t%0,%1,%2\";
 }"
   [(set_attr "type"	"arith")
@@ -8804,7 +8804,7 @@ move\\t%0,%z4\\n\\
   "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
   "*
 {
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
   return \"sltu\\t%0,%1,%2\";
 }"
   [(set_attr "type"	"arith")
@@ -9514,8 +9514,8 @@ move\\t%0,%z4\\n\\
 	}
 
       emit_call_insn (gen_call_internal0 (operands[0], operands[1],
-					  gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
-
+					  gen_rtx_REG (SImode,
+						       GP_REG_FIRST + 31)));
       DONE;
     }
 }")
@@ -9694,7 +9694,7 @@ move\\t%0,%z4\\n\\
 			  (XEXP (XVECEXP (operands[0], 0, 0), 0),
 			   operands[1], operands[2],
 			   XEXP (XVECEXP (operands[0], 0, 1), 0),
-			   gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
+			   gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
 	  DONE;
 	}
 
@@ -9704,7 +9704,8 @@ move\\t%0,%z4\\n\\
 	operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
 
       emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
-					        gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
+					        gen_rtx_REG (SImode,
+							     GP_REG_FIRST + 31)));
 
       DONE;
     }
@@ -9945,7 +9946,7 @@ move\\t%0,%z4\\n\\
 ;;   "
 ;; {
 ;;   operands[0] = gen_reg_rtx (SImode);
-;;   operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx);
+;;   operands[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
 ;;   MEM_VOLATILE_P (operands[1]) = TRUE;
 ;; 
 ;;   /* fall through and generate default code */