* config/m32c/addsub.md (addqi3): Disparage a0/a1.

(addpsi3): Expand to include memory operands.  Remove
reload-specific splits.
* config/m32c/bitops.md (bset_qi, bset_hi, bclr_qi): New.
(andqi3_16, andhi3_16, iorqi3_16, iorhi3_16): New.
(andqi3_24, andhi3_24, iorqi3_24, iorhi3_24): New.
(andqi3, andhi3, iorqi3, iorhi3): Convert to expanders.
(shift1_qi, shift1_hi, insv): New.
* config/m32c/cond.md (cbranchqi4, cbranchhi4): Remove.
(cbranch<mode>4, stzx_16, stzx_24_<mode>, stzx_reversed,
cmp<mode>, b<code>, s<code>, s<code>_24, movqicc, movhicc,
cond_to_int): New.
* config/m32c/m32c-protos.h: Update as needed.
* config/m32c/m32c.c (m32c_reg_class_from_constraint): Don't
default the Rcr, Rcl, Raw, and Ral constraints.  Add Ra0 and Ra1.
Fail for unrecognized R* constraints.
(m32c_cannot_change_mode_class): Be more picky about pseudos.
(m32c_const_ok_for_constraint_p): Add Imb, Imw, and I00.
(m32c_extra_constraint_p2): Allow (mem (plus (plus fb int) int)).
Add Sp constraint.
(m32c_init_libfuncs): New.
(m32c_legitimate_address_p): Add debug wrapper.
(m32c_rtx_costs): New.
(m32c_address_cost): New.
(conversions): Add 'B' prefix.
(m32c_print_operand): 'h' and 'H' pick lower and upper halves of
operands, or word regnames for QI operands.  'B' prints bit
position.
(m32c_expand_setmemhi): New.
(m32c_expand_movmemhi): New.
(m32c_expand_movstr): New.
(m32c_expand_cmpstr): New.
(m32c_prepare_shift): Shift counts are limited to 16 bits at a time.
(m32c_expand_neg_mulpsi3): Handle non-ints.
(m32c_cmp_flg_0): New.
(m32c_expand_movcc): New.
(m32c_expand_insv): New.
(m32c_scc_pattern): New.
* config/m32c/m32c.h (reg classes): Add AO_REGS and A1_REGS.  Take
a0/a1 out of SIregs.
(STORE_FLAG_VALUE): New.
* config/m32c/m32c.md: Add unspecs for string moves.  Define various mode and
code macros.
(no_insn): New.
* config/m32c/mov.md: Make constraints more liberal.
(zero_extendqihi2): Optimize r0/r1 case.
* config/m32c/muldiv.md (mulpsi3): Check for intvals.
* config/m32c/predicates.md (m32c_any_operand): New.
(m32c_nonimmediate_operand): New.
(m32c_hl_operand): New.
(m32c_r3_operand): New.
(ap_operand): New.
(ma_operand): New.
(memsym_operand): New.
(memimmed_operand): New.
(a_qi_operand): New.
(m32c_eqne_operator): New.
(m32c_1bit8_operand): New.
(m32c_1bit16_operand): New.
(m32c_1mask8_operand): New.
(m32c_1mask16_operand): New.
* config/m32c/blkmov.md: New file.
* config/m32c/t-m32c (MD_FILES): Add blkmov.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@111859 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 78 insertions, 7 deletions

diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md
index c3b44b812d0..5b9549c6f7b 100644
--- a/gcc/config/m32c/predicates.md
+++ b/gcc/config/m32c/predicates.md
@@ -22,6 +22,19 @@
 
 ;; Predicates
 
+; TRUE for any valid operand.  We do this because general_operand
+; refuses to match volatile memory refs.
+
+(define_predicate "m32c_any_operand"
+  (ior (match_operand 0 "general_operand")
+       (match_operand 1 "memory_operand")))
+
+; Likewise for nonimmediate_operand.
+
+(define_predicate "m32c_nonimmediate_operand"
+  (ior (match_operand 0 "nonimmediate_operand")
+       (match_operand 1 "memory_operand")))
+
 ; TRUE if the operand is a pseudo-register.
 (define_predicate "m32c_pseudo"
   (ior (and (match_code "reg")
@@ -63,12 +76,25 @@
        (and (match_code "reg")
 	    (match_test "REGNO(op) == R1_REGNO"))))
 
+; TRUE for HL_CLASS (r0 or r1)
+(define_predicate "m32c_hl_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) == R0_REGNO || REGNO(op) == R1_REGNO"))))
+
+
 ; TRUE for r2
 (define_predicate "m32c_r2_operand"
   (ior (match_operand 0 "m32c_pseudo" "")
        (and (match_code "reg")
 	    (match_test "REGNO(op) == R2_REGNO"))))
 
+; TRUE for r3
+(define_predicate "m32c_r3_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) == R3_REGNO"))))
+
 ; TRUE for any general operand except r2.
 (define_predicate "m32c_notr2_operand"
   (and (match_operand 0 "general_operand")
@@ -89,9 +115,14 @@
 
 ; TRUE for $a0 or $a1.
 (define_predicate "a_operand"
-  (match_code "reg")
-  "return (REGNO (op) == A0_REGNO
-           || REGNO (op) == A1_REGNO);")
+  (and (match_code "reg")
+       (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO")))
+
+; TRUE for $a0 or $a1 or a pseudo
+(define_predicate "ap_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO"))))
 
 ; TRUE for r0 through r3, or a0 or a1.
 (define_predicate "ra_operand"
@@ -112,7 +143,7 @@
 
 ; TRUE for memory, r0..r3, a0..a1, or immediates.
 (define_predicate "mrai_operand"
-  (and (and (match_operand 0 "general_operand" "")
+  (and (and (match_operand 0 "m32c_any_operand" "")
 	    (not (match_operand 1 "cr_operand" "")))
        (not (match_operand 2 "m32c_wide_subreg" ""))))
 
@@ -126,7 +157,22 @@
   (and (match_operand 0 "mra_operand" "")
        (not (match_operand 1 "a_operand" ""))))
 
-; TRUE for r1h.  This complicated since r1h isn't a register GCC
+; TRUE for a0..a1 or memory.
+(define_predicate "ma_operand"
+  (ior (match_operand 0 "a_operand" "")
+       (match_operand 1 "memory_operand" "")))
+
+; TRUE for memory operands that are not indexed
+(define_predicate "memsym_operand"
+  (and (match_operand 0 "memory_operand" "")
+       (match_test "m32c_extra_constraint_p (op, 'S', \"Si\")")))
+
+; TRUE for memory operands with small integer addresses
+(define_predicate "memimmed_operand"
+  (and (match_operand 0 "memory_operand" "")
+       (match_test "m32c_extra_constraint_p (op, 'S', \"Sp\")")))
+
+; TRUE for r1h.  This is complicated since r1h isn't a register GCC
 ; normally knows about.
 (define_predicate "r1h_operand"
   (match_code "zero_extract")
@@ -175,19 +221,26 @@
 
 ; These two are only for movqi - no subreg limit
 (define_predicate "mra_qi_operand"
-  (and (and (match_operand 0 "nonimmediate_operand" "")
+  (and (and (match_operand 0 "m32c_nonimmediate_operand" "")
 	    (not (match_operand 1 "cr_operand" "")))
        (not (match_operand 1 "m32c_r2r3a_operand" ""))))
 
 (define_predicate "mrai_qi_operand"
-  (and (and (match_operand 0 "general_operand" "")
+  (and (and (match_operand 0 "m32c_any_operand" "")
 	    (not (match_operand 1 "cr_operand" "")))
        (not (match_operand 1 "m32c_r2r3a_operand" ""))))
 
+(define_predicate "a_qi_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (match_operand 1 "a_operand" "")))
+
 ; TRUE for comparisons we support.
 (define_predicate "m32c_cmp_operator"
   (match_code "eq,ne,gt,gtu,lt,ltu,ge,geu,le,leu"))
 
+(define_predicate "m32c_eqne_operator"
+  (match_code "eq,ne"))
+
 ; TRUE for mem0
 (define_predicate "m32c_mem0_operand"
   (ior (match_operand 0 "m32c_pseudo" "")
@@ -204,3 +257,21 @@
 (define_predicate "m32c_psi_scale"
   (and (match_operand 0 "const_int_operand")
        (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")")))
+
+; TRUE for one bit set (bit) or clear (mask) out of N bits.
+
+(define_predicate "m32c_1bit8_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")")))
+
+(define_predicate "m32c_1bit16_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilw\")")))
+
+(define_predicate "m32c_1mask8_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Imb\")")))
+
+(define_predicate "m32c_1mask16_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Imw\")")))