* config/alpha/alpha.c (alpha_preferred_reload_class,

	alpha_secondary_reload, alpha_emit_set_const_1, function_value,
	alpha_output_mi_thunk_osf): Avoid C++ keywords.
	* config/arm/arm.c (output_move_vfp, output_move_neon): Likewise.
	* config/arm/arm.md: Likewise.
	* config/avr/avr-protos.h (preferred_reload_class,
	test_hard_reg_class, avr_simplify_comparison_p,
	out_shift_with_cnt, class_max_nregs): Likewise.
	* config/avr/avr.c (class_max_nregs, avr_simplify_comparison_p,
	output_movqi, output_movhi, output_movsisf, out_shift_with_cnt,
	preferred_reload_class, test_hard_reg_class): Likewise.
	* config/bfin/bfin.c (legitimize_pic_address, hard_regno_mode_ok,
	bfin_memory_move_cost, bfin_secondary_reload,
	bfin_output_mi_thunk): Likewise.
	* config/crx/crx.c (crx_secondary_reload_class,
	crx_memory_move_cost): Likewise.
	* config/frv/frv-protos.h (frv_secondary_reload_class,
	frv_class_likely_spilled_p, frv_class_max_nregs): Likewise.
	* config/frv/frv.c (frv_override_options, frv_alloc_temp_reg,
	frv_secondary_reload_class, frv_class_likely_spilled_p,
	frv_class_max_nregs): Likewise.
	* config/h8300/h8300.c (h8300_classify_operand,
	h8300_unary_length, h8300_bitfield_length, h8300_asm_insn_count):
	Likewise.
	* config/i386/winnt.c (i386_pe_declare_function_type): Likewise.
	* config/ia64/ia64.c (ia64_preferred_reload_class,
	ia64_secondary_reload_class, ia64_output_mi_thunk): Likewise.
	* config/iq2000/iq2000.c (gen_int_relational): Likewise.
	* config/m32c/m32c.c (class_can_hold_mode, m32c_output_compare):
	Likewise.
	* config/m68hc11/m68hc11.c (preferred_reload_class,
	m68hc11_memory_move_cost): Likewise.
	* config/mcore/mcore.c (mcore_secondary_reload_class,
	mcore_reload_class): Likewise.
	* config/mips/mips.c (mips_hard_regno_mode_ok_p,
	mips_class_max_nregs, mips_cannot_change_mode_class,
	mips_preferred_reload_class, mips_secondary_reload_class,
	mips_output_mi_thunk): Likewise.
	* config/mmix/mmix.c (mmix_preferred_reload_class,
	mmix_preferred_output_reload_class, mmix_secondary_reload_class):
	Likewise.
	* config/mn10300/mn10300.c (mn10300_secondary_reload_class):
	Likewise.
	* config/pa/pa.c (pa_secondary_reload, pa_combine_instructions,
	pa_can_combine_p, pa_cannot_change_mode_class): Likewise.
	* config/pa/pa.h (LEGITIMIZE_RELOAD_ADDRESS): Likewise.
	* config/rs6000/rs6000.c (paired_expand_vector_init,
	rs6000_secondary_reload_class, rs6000_output_mi_thunk,
	compare_section_name, rs6000_memory_move_cost): Likewise.
	* config/s390/s390.c (s390_emit_compare_and_swap,
	s390_preferred_reload_class, s390_secondary_reload,
	legitimize_pic_address, legitimize_tls_address,
	legitimize_reload_address, s390_expand_cs_hqi, s390_expand_atomic,
	s390_class_max_nregs): Likewise.
	* config/s390/s390.h (LEGITIMIZE_RELOAD_ADDRESS): Likewise.
	* config/s390/s390.md: Likewise.
	* config/score/score-protos.h (score_secondary_reload_class,
	score_preferred_reload_class): Likewise.
	* config/score/score.c (score_preferred_reload_class,
	score_secondary_reload_class): Likewise.
	* config/score/score3.c (score3_output_mi_thunk,
	score3_preferred_reload_class, score3_secondary_reload_class,
	score3_hard_regno_mode_ok): Likewise.
	* config/score/score3.h (score3_preferred_reload_class,
	score3_secondary_reload_class): Likewise.
	* config/score/score7.c (score7_output_mi_thunk,
	score7_preferred_reload_class, score7_secondary_reload_class,
	score7_hard_regno_mode_ok): Likewise.
	* config/score/score7.h (score7_preferred_reload_class,
	score7_secondary_reload_class): Likewise.
	* config/sh/sh.c (prepare_move_operands, output_far_jump,
	output_branchy_insn, add_constant, gen_block_redirect,
	sh_insn_length_adjustment, sh_cannot_change_mode_class,
	sh_output_mi_thunk, replace_n_hard_rtx, sh_secondary_reload):
	Likewise.
	* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
	* config/stormy16/stormy16.c (xstormy16_output_cbranch_hi,
	xstormy16_output_cbranch_si, xstormy16_secondary_reload_class,
	xstormy16_preferred_reload_class): Likewise.
	* config/xtensa/xtensa.c (xtensa_expand_compare_and_swap,
	xtensa_expand_atomic, override_options,
	xtensa_preferred_reload_class, xtensa_secondary_reload_class):
	Likewise.
	* reorg.c (try_merge_delay_insns): Likewise.
	* tree.c (merge_dllimport_decl_attributes): Likewise.

	* config/frv/frv.c (frv_print_operand): Change isalpha to ISALPHA.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@138813 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 43 insertions, 43 deletions

diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 07e8eaae928..7fa2e22f094 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -651,83 +651,83 @@ frv_override_options (void)
 
   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
     {
-      enum reg_class class;
+      enum reg_class rclass;
 
       if (GPR_P (regno))
 	{
 	  int gpr_reg = regno - GPR_FIRST;
 
 	  if (gpr_reg == GR8_REG)
-	    class = GR8_REGS;
+	    rclass = GR8_REGS;
 
 	  else if (gpr_reg == GR9_REG)
-	    class = GR9_REGS;
+	    rclass = GR9_REGS;
 
 	  else if (gpr_reg == GR14_REG)
-	    class = FDPIC_FPTR_REGS;
+	    rclass = FDPIC_FPTR_REGS;
 
 	  else if (gpr_reg == FDPIC_REGNO)
-	    class = FDPIC_REGS;
+	    rclass = FDPIC_REGS;
 
 	  else if ((gpr_reg & 3) == 0)
-	    class = QUAD_REGS;
+	    rclass = QUAD_REGS;
 
 	  else if ((gpr_reg & 1) == 0)
-	    class = EVEN_REGS;
+	    rclass = EVEN_REGS;
 
 	  else
-	    class = GPR_REGS;
+	    rclass = GPR_REGS;
 	}
 
       else if (FPR_P (regno))
 	{
 	  int fpr_reg = regno - GPR_FIRST;
 	  if ((fpr_reg & 3) == 0)
-	    class = QUAD_FPR_REGS;
+	    rclass = QUAD_FPR_REGS;
 
 	  else if ((fpr_reg & 1) == 0)
-	    class = FEVEN_REGS;
+	    rclass = FEVEN_REGS;
 
 	  else
-	    class = FPR_REGS;
+	    rclass = FPR_REGS;
 	}
 
       else if (regno == LR_REGNO)
-	class = LR_REG;
+	rclass = LR_REG;
 
       else if (regno == LCR_REGNO)
-	class = LCR_REG;
+	rclass = LCR_REG;
 
       else if (ICC_P (regno))
-	class = ICC_REGS;
+	rclass = ICC_REGS;
 
       else if (FCC_P (regno))
-	class = FCC_REGS;
+	rclass = FCC_REGS;
 
       else if (ICR_P (regno))
-	class = ICR_REGS;
+	rclass = ICR_REGS;
 
       else if (FCR_P (regno))
-	class = FCR_REGS;
+	rclass = FCR_REGS;
 
       else if (ACC_P (regno))
 	{
 	  int r = regno - ACC_FIRST;
 	  if ((r & 3) == 0)
-	    class = QUAD_ACC_REGS;
+	    rclass = QUAD_ACC_REGS;
 	  else if ((r & 1) == 0)
-	    class = EVEN_ACC_REGS;
+	    rclass = EVEN_ACC_REGS;
 	  else
-	    class = ACC_REGS;
+	    rclass = ACC_REGS;
 	}
 
       else if (ACCG_P (regno))
-	class = ACCG_REGS;
+	rclass = ACCG_REGS;
 
       else
-	class = NO_REGS;
+	rclass = NO_REGS;
 
-      regno_reg_class[regno] = class;
+      regno_reg_class[regno] = rclass;
     }
 
   /* Check for small data option */
@@ -1539,14 +1539,14 @@ frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 static rtx
 frv_alloc_temp_reg (
      frv_tmp_reg_t *info,	/* which registers are available */
-     enum reg_class class,	/* register class desired */
+     enum reg_class rclass,	/* register class desired */
      enum machine_mode mode,	/* mode to allocate register with */
      int mark_as_used,		/* register not available after allocation */
      int no_abort)		/* return NULL instead of aborting */
 {
-  int regno = info->next_reg[ (int)class ];
+  int regno = info->next_reg[ (int)rclass ];
   int orig_regno = regno;
-  HARD_REG_SET *reg_in_class = &reg_class_contents[ (int)class ];
+  HARD_REG_SET *reg_in_class = &reg_class_contents[ (int)rclass ];
   int i, nr;
 
   for (;;)
@@ -1565,7 +1565,7 @@ frv_alloc_temp_reg (
     }
 
   nr = HARD_REGNO_NREGS (regno, mode);
-  info->next_reg[ (int)class ] = regno + nr;
+  info->next_reg[ (int)rclass ] = regno + nr;
 
   if (mark_as_used)
     for (i = 0; i < nr; i++)
@@ -2777,7 +2777,7 @@ frv_print_operand (FILE * file, rtx x, int code)
   HOST_WIDE_INT value;
   int offset;
 
-  if (code != 0 && !isalpha (code))
+  if (code != 0 && !ISALPHA (code))
     value = 0;
 
   else if (GET_CODE (x) == CONST_INT)
@@ -6300,11 +6300,11 @@ frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
    You should define these macros to indicate to the reload phase that it may
    need to allocate at least one register for a reload in addition to the
    register to contain the data.  Specifically, if copying X to a register
-   CLASS in MODE requires an intermediate register, you should define
+   RCLASS in MODE requires an intermediate register, you should define
    `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
    whose registers can be used as intermediate registers or scratch registers.
 
-   If copying a register CLASS in MODE to X requires an intermediate or scratch
+   If copying a register RCLASS in MODE to X requires an intermediate or scratch
    register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
    largest register class required.  If the requirements for input and output
    reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
@@ -6312,7 +6312,7 @@ frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
 
    The values returned by these macros are often `GENERAL_REGS'.  Return
    `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
-   to or from a register of CLASS in MODE without requiring a scratch register.
+   to or from a register of RCLASS in MODE without requiring a scratch register.
    Do not define this macro if it would always return `NO_REGS'.
 
    If a scratch register is required (either with or without an intermediate
@@ -6323,7 +6323,7 @@ frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
 
    Define constraints for the reload register and scratch register that contain
    a single register class.  If the original reload register (whose class is
-   CLASS) can meet the constraint given in the pattern, the value returned by
+   RCLASS) can meet the constraint given in the pattern, the value returned by
    these macros is used for the class of the scratch register.  Otherwise, two
    additional reload registers are required.  Their classes are obtained from
    the constraints in the insn pattern.
@@ -6341,14 +6341,14 @@ frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
    This case often occurs between floating-point and general registers.  */
 
 enum reg_class
-frv_secondary_reload_class (enum reg_class class,
+frv_secondary_reload_class (enum reg_class rclass,
                             enum machine_mode mode ATTRIBUTE_UNUSED,
                             rtx x,
                             int in_p ATTRIBUTE_UNUSED)
 {
   enum reg_class ret;
 
-  switch (class)
+  switch (rclass)
     {
     default:
       ret = NO_REGS;
@@ -6405,10 +6405,10 @@ frv_secondary_reload_class (enum reg_class class,
 
 
 /* A C expression whose value is nonzero if pseudos that have been assigned to
-   registers of class CLASS would likely be spilled because registers of CLASS
+   registers of class RCLASS would likely be spilled because registers of RCLASS
    are needed for spill registers.
 
-   The default value of this macro returns 1 if CLASS has exactly one register
+   The default value of this macro returns 1 if RCLASS has exactly one register
    and zero otherwise.  On most machines, this default should be used.  Only
    define this macro to some other expression if pseudo allocated by
    `local-alloc.c' end up in memory because their hard registers were needed
@@ -6420,9 +6420,9 @@ frv_secondary_reload_class (enum reg_class class,
    register allocation.  */
 
 int
-frv_class_likely_spilled_p (enum reg_class class)
+frv_class_likely_spilled_p (enum reg_class rclass)
 {
-  switch (class)
+  switch (rclass)
     {
     default:
       break;
@@ -6686,11 +6686,11 @@ frv_hard_regno_nregs (int regno, enum machine_mode mode)
 
 
 /* A C expression for the maximum number of consecutive registers of
-   class CLASS needed to hold a value of mode MODE.
+   class RCLASS needed to hold a value of mode MODE.
 
    This is closely related to the macro `HARD_REGNO_NREGS'.  In fact, the value
-   of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
-   `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
+   of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
+   `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
 
    This macro helps control the handling of multiple-word values in
    the reload pass.
@@ -6698,9 +6698,9 @@ frv_hard_regno_nregs (int regno, enum machine_mode mode)
    This declaration is required.  */
 
 int
-frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
+frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
 {
-  if (class == ACCG_REGS)
+  if (rclass == ACCG_REGS)
     /* An N-byte value requires N accumulator guards.  */
     return GET_MODE_SIZE (mode);
   else