summaryrefslogtreecommitdiffstats
path: root/sim
Commit message (Expand)AuthorAgeFilesLines
...
* * gencode.c (build_instruction): Handle "pext5" according toJeff Law1997-07-022-1/+4
* * gencode.c (build_instruction): Handle "ppac5" according toJeff Law1997-07-022-1/+6
* * interp.c (sim_engine_run): Reset the ZERO register to zeroJeff Law1997-07-022-23/+40
* * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.Jeff Law1997-07-022-3/+20
* Add test for dbt/rtd instructionsAndrew Cagney1997-06-271-0/+38
* * interp.c (sim_resume): Clear State.exited.Jeff Law1997-06-241-0/+1
* * simops.c: Fix thinko in last change.Jeff Law1997-06-122-1/+5
* * simops.c: "call" stores the callee saved registers into theJeff Law1997-06-102-53/+55
* * simops.c: Fix return address computation for "call" instructions.Jeff Law1997-06-102-2/+10
* Open in binary mode when available.Andrew Cagney1997-06-061-0/+8
* Clean up formatting of instruction traces.Andrew Cagney1997-06-061-0/+33
* Verify magic number of simulator struct.Andrew Cagney1997-06-051-0/+4
* Initialize the sim-engine module.Andrew Cagney1997-06-041-0/+12
* o Fixes to repeated watchpointsAndrew Cagney1997-06-033-110/+228
* o Fix padd insnAndrew Cagney1997-06-021-8/+12
* Add assembler information to igen input files.Andrew Cagney1997-05-307-153/+309
* Fix subu immed - was incorrectly using unsigned.Andrew Cagney1997-05-293-1/+10
* Add a simple dissasembler to igenAndrew Cagney1997-05-294-38/+740
* Fix watching PC for 64bit (mips) target.Andrew Cagney1997-05-272-42/+146
* Extend xor-endian and per-cpu support in core module.Andrew Cagney1997-05-2711-63/+294
* Preliminary suport for xor-endian suport in core module.Andrew Cagney1997-05-236-79/+181
* Incorrect test for zero-r0 code gen.Andrew Cagney1997-05-232-2/+12
* Enumerate longjmp's return type.Andrew Cagney1997-05-231-0/+5
* ifdef out uses of simSTOP, simSTEP and simBE when DEBUG is defined.Gavin Romig-Koch1997-05-222-0/+9
* Change longjmp param/setjmp return value used for simulator restart from 0 to 2.Gavin Romig-Koch1997-05-223-6/+27
* * interp.c (sim_resume): Add missing case in big switchJeff Law1997-05-222-0/+6
* Watchpoint interface.Andrew Cagney1997-05-2116-817/+1486
* * interp.c: Replace all references to load_mem and store_memJeff Law1997-05-203-340/+295
* Part II of adding callback argument to sim_open(). Update all theAndrew Cagney1997-05-207-56/+48
* Depreciate sim_set_callbacks() function. Set simulator callbacksAndrew Cagney1997-05-203-18/+19
* Make getpid, kill supported system callsMichael Meissner1997-05-196-39/+157
* * interp.c (dispatch): Make this an inline function.Jeff Law1997-05-193-7/+10
* Graft sim/common event and other code onto the mips simulator.Andrew Cagney1997-05-195-220/+196
* Update.Andrew Cagney1997-05-191-3/+8
* Make simulator event-queue manager a bit more signal safe.Andrew Cagney1997-05-193-0/+26
* o Implement generic halt/restart/abort module.Andrew Cagney1997-05-1918-368/+1406
* Pacify gcc.Andrew Cagney1997-05-191-0/+4
* * interp.c (load_mem_big): Remove function. It's now a macroJeff Law1997-05-182-26/+34
* Treat infinities like normal numbers for purposes of comparisonsMichael Meissner1997-05-172-6/+11
* * callback.c (os_close): Mark the descriptor as beingJeff Law1997-05-162-6/+127
* * interp.c (load_mem): If we get a load from an out of rangeJeff Law1997-05-162-0/+18
* o Make tic80 insn file more `cache ready'Andrew Cagney1997-05-169-174/+218
* Remove some of the flake from the c80 floating point.Andrew Cagney1997-05-155-50/+617
* More floating point operations.Andrew Cagney1997-05-153-21/+137
* Fix double conversion problem.Andrew Cagney1997-05-154-45/+76
* Passify gcc's warnings.Andrew Cagney1997-05-152-1/+5
* Make columns line up for fpu operation tracingMichael Meissner1997-05-142-7/+13
* Make sure r0 == 0; Return EINVAL for system calls that are defined but not pr...Michael Meissner1997-05-133-0/+37
* Remove ANNULed cycle - was confusing gdb.Andrew Cagney1997-05-134-56/+54
* Fix ld/st tracingMichael Meissner1997-05-122-2/+6
OpenPOWER on IntegriCloud