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2_24-branch'.
Sprout from master 2013-09-18 10:39:38 UTC Tristan Gingold <gingold@adacore.com> 'binutils/'
Cherrypick from cygnus 1999-05-03 07:29:11 UTC Richard Henderson <rth@redhat.com> '19990502 sourceware import':
README
bfd/doc/doc.str
bfd/stamp-h.in
binutils/stamp-h.in
binutils/testsuite/binutils-all/bintest.s
binutils/testsuite/binutils-all/hppa/addendbug.s
config/mt-d30v
config/mt-ospace
etc/add-log.el
etc/add-log.vi
etc/configbuild.ein
etc/configbuild.fig
etc/configbuild.jin
etc/configbuild.tin
etc/configdev.ein
etc/configdev.fig
etc/configdev.jin
etc/configdev.tin
gas/stamp-h.in
gas/testsuite/gas/all/align.s
gas/testsuite/gas/all/comment.s
gas/testsuite/gas/all/diff1.s
gas/testsuite/gas/all/float.s
gas/testsuite/gas/all/itbl
gas/testsuite/gas/all/itbl.s
gas/testsuite/gas/all/p1480.s
gas/testsuite/gas/all/struct.d
gas/testsuite/gas/all/struct.s
gas/testsuite/gas/all/x930509.s
gas/testsuite/gas/arc/alias.d
gas/testsuite/gas/arc/alias.s
gas/testsuite/gas/arc/branch.d
gas/testsuite/gas/arc/branch.s
gas/testsuite/gas/arc/flag.s
gas/testsuite/gas/arc/insn3.d
gas/testsuite/gas/arc/insn3.s
gas/testsuite/gas/arc/math.d
gas/testsuite/gas/arc/math.s
gas/testsuite/gas/arc/sshift.d
gas/testsuite/gas/arc/sshift.s
gas/testsuite/gas/arm/le-fpconst.s
gas/testsuite/gas/d30v/align.d
gas/testsuite/gas/d30v/align.s
gas/testsuite/gas/d30v/array.d
gas/testsuite/gas/d30v/array.s
gas/testsuite/gas/d30v/bittest.d
gas/testsuite/gas/d30v/bittest.s
gas/testsuite/gas/d30v/guard-debug.s
gas/testsuite/gas/d30v/guard.d
gas/testsuite/gas/d30v/guard.s
gas/testsuite/gas/d30v/inst.s
gas/testsuite/gas/d30v/label-debug.d
gas/testsuite/gas/d30v/label-debug.s
gas/testsuite/gas/d30v/label.d
gas/testsuite/gas/d30v/label.s
gas/testsuite/gas/d30v/mul.d
gas/testsuite/gas/d30v/mul.s
gas/testsuite/gas/d30v/opt.d
gas/testsuite/gas/d30v/opt.s
gas/testsuite/gas/d30v/reloc.d
gas/testsuite/gas/d30v/reloc.s
gas/testsuite/gas/d30v/serial.s
gas/testsuite/gas/d30v/serial2.s
gas/testsuite/gas/d30v/serial2O.s
gas/testsuite/gas/d30v/warn_oddreg.l
gas/testsuite/gas/d30v/warn_oddreg.s
gas/testsuite/gas/fr30/allinsn.d
gas/testsuite/gas/fr30/allinsn.s
gas/testsuite/gas/h8300/addsub.s
gas/testsuite/gas/h8300/addsubh.s
gas/testsuite/gas/h8300/addsubs.s
gas/testsuite/gas/h8300/bitops1.s
gas/testsuite/gas/h8300/bitops1h.s
gas/testsuite/gas/h8300/bitops1s.s
gas/testsuite/gas/h8300/bitops2.s
gas/testsuite/gas/h8300/bitops2h.s
gas/testsuite/gas/h8300/bitops2s.s
gas/testsuite/gas/h8300/bitops3.s
gas/testsuite/gas/h8300/bitops3h.s
gas/testsuite/gas/h8300/bitops3s.s
gas/testsuite/gas/h8300/bitops4.s
gas/testsuite/gas/h8300/bitops4h.s
gas/testsuite/gas/h8300/bitops4s.s
gas/testsuite/gas/h8300/cbranch.s
gas/testsuite/gas/h8300/cbranchh.s
gas/testsuite/gas/h8300/cbranchs.s
gas/testsuite/gas/h8300/compare.s
gas/testsuite/gas/h8300/compareh.s
gas/testsuite/gas/h8300/compares.s
gas/testsuite/gas/h8300/decimal.s
gas/testsuite/gas/h8300/decimalh.s
gas/testsuite/gas/h8300/decimals.s
gas/testsuite/gas/h8300/divmul.s
gas/testsuite/gas/h8300/divmulh.s
gas/testsuite/gas/h8300/divmuls.s
gas/testsuite/gas/h8300/extendh.s
gas/testsuite/gas/h8300/extends.s
gas/testsuite/gas/h8300/incdec.s
gas/testsuite/gas/h8300/incdech.s
gas/testsuite/gas/h8300/incdecs.s
gas/testsuite/gas/h8300/logical.s
gas/testsuite/gas/h8300/logicalh.s
gas/testsuite/gas/h8300/logicals.s
gas/testsuite/gas/h8300/misc.s
gas/testsuite/gas/h8300/misch.s
gas/testsuite/gas/h8300/miscs.s
gas/testsuite/gas/h8300/mov32bug.s
gas/testsuite/gas/h8300/movb.s
gas/testsuite/gas/h8300/movbh.s
gas/testsuite/gas/h8300/movbs.s
gas/testsuite/gas/h8300/movlh.s
gas/testsuite/gas/h8300/movls.s
gas/testsuite/gas/h8300/movw.s
gas/testsuite/gas/h8300/movwh.s
gas/testsuite/gas/h8300/movws.s
gas/testsuite/gas/h8300/pushpop.s
gas/testsuite/gas/h8300/pushpoph.s
gas/testsuite/gas/h8300/pushpops.s
gas/testsuite/gas/h8300/rotsh.s
gas/testsuite/gas/h8300/rotshh.s
gas/testsuite/gas/h8300/rotshs.s
gas/testsuite/gas/hppa/basic/weird.s
gas/testsuite/gas/hppa/parse/appbug.s
gas/testsuite/gas/hppa/parse/nosubspace.s
gas/testsuite/gas/hppa/parse/spacebug.s
gas/testsuite/gas/hppa/parse/ssbug.s
gas/testsuite/gas/hppa/reloc/reduce2.s
gas/testsuite/gas/hppa/unsorted/align3.s
gas/testsuite/gas/hppa/unsorted/align4.s
gas/testsuite/gas/hppa/unsorted/globalbug.s
gas/testsuite/gas/hppa/unsorted/ss_align.s
gas/testsuite/gas/ieee-fp/x930509a.s
gas/testsuite/gas/m32r/allinsn.s
gas/testsuite/gas/m32r/fslot.d
gas/testsuite/gas/m32r/fslot.s
gas/testsuite/gas/m32r/high-1.s
gas/testsuite/gas/m32r/outofrange.s
gas/testsuite/gas/m32r/relax-1.s
gas/testsuite/gas/m32r/uppercase.s
gas/testsuite/gas/m68k-coff/p2389.s
gas/testsuite/gas/m68k-coff/p2389a.s
gas/testsuite/gas/m68k-coff/p2430.s
gas/testsuite/gas/m68k-coff/p2430a.s
gas/testsuite/gas/m68k-coff/t1.s
gas/testsuite/gas/m68k/bitfield.d
gas/testsuite/gas/m68k/bitfield.s
gas/testsuite/gas/m68k/cas.d
gas/testsuite/gas/m68k/cas.s
gas/testsuite/gas/m68k/disperr.s
gas/testsuite/gas/m68k/fmoveml.d
gas/testsuite/gas/m68k/fmoveml.s
gas/testsuite/gas/m68k/link.d
gas/testsuite/gas/m68k/link.s
gas/testsuite/gas/m68k/op68000.d
gas/testsuite/gas/m68k/operands.d
gas/testsuite/gas/m68k/operands.s
gas/testsuite/gas/m68k/p2410.s
gas/testsuite/gas/m68k/p2663.s
gas/testsuite/gas/m68k/pic1.s
gas/testsuite/gas/m68k/t2.d
gas/testsuite/gas/m68k/t2.s
gas/testsuite/gas/macros/err.s
gas/testsuite/gas/mips/abs.s
gas/testsuite/gas/mips/add.s
gas/testsuite/gas/mips/break20.s
gas/testsuite/gas/mips/div.s
gas/testsuite/gas/mips/itbl
gas/testsuite/gas/mips/itbl.s
gas/testsuite/gas/mips/lb.s
gas/testsuite/gas/mips/mips16.s
gas/testsuite/gas/mips/mul.s
gas/testsuite/gas/mips/sb.s
gas/testsuite/gas/mips/trap20.s
gas/testsuite/gas/mips/trunc.s
gas/testsuite/gas/mips/uld.s
gas/testsuite/gas/mips/ulh-pic.s
gas/testsuite/gas/mips/ulh.s
gas/testsuite/gas/mips/ulw.s
gas/testsuite/gas/mips/usd.s
gas/testsuite/gas/mips/ush.s
gas/testsuite/gas/mips/usw.s
gas/testsuite/gas/mn10200/add.s
gas/testsuite/gas/mn10200/bcc.s
gas/testsuite/gas/mn10200/bccx.s
gas/testsuite/gas/mn10200/bit.s
gas/testsuite/gas/mn10200/cmp.s
gas/testsuite/gas/mn10200/ext.s
gas/testsuite/gas/mn10200/logical.s
gas/testsuite/gas/mn10200/mov1.s
gas/testsuite/gas/mn10200/mov2.s
gas/testsuite/gas/mn10200/mov3.s
gas/testsuite/gas/mn10200/mov4.s
gas/testsuite/gas/mn10200/movb.s
gas/testsuite/gas/mn10200/movbu.s
gas/testsuite/gas/mn10200/movx.s
gas/testsuite/gas/mn10200/muldiv.s
gas/testsuite/gas/mn10200/other.s
gas/testsuite/gas/mn10200/shift.s
gas/testsuite/gas/mn10200/sub.s
gas/testsuite/gas/mn10300/add.s
gas/testsuite/gas/mn10300/bcc.s
gas/testsuite/gas/mn10300/bit.s
gas/testsuite/gas/mn10300/cmp.s
gas/testsuite/gas/mn10300/ext.s
gas/testsuite/gas/mn10300/extend.s
gas/testsuite/gas/mn10300/logical.s
gas/testsuite/gas/mn10300/loop.s
gas/testsuite/gas/mn10300/mov1.s
gas/testsuite/gas/mn10300/mov2.s
gas/testsuite/gas/mn10300/mov3.s
gas/testsuite/gas/mn10300/mov4.s
gas/testsuite/gas/mn10300/movbu.s
gas/testsuite/gas/mn10300/movhu.s
gas/testsuite/gas/mn10300/movm.s
gas/testsuite/gas/mn10300/muldiv.s
gas/testsuite/gas/mn10300/other.s
gas/testsuite/gas/mn10300/shift.s
gas/testsuite/gas/mn10300/sub.s
gas/testsuite/gas/mn10300/udf.s
gas/testsuite/gas/mri/char.d
gas/testsuite/gas/mri/char.s
gas/testsuite/gas/mri/comment.d
gas/testsuite/gas/mri/comment.s
gas/testsuite/gas/mri/common.d
gas/testsuite/gas/mri/common.s
gas/testsuite/gas/mri/constants.d
gas/testsuite/gas/mri/constants.s
gas/testsuite/gas/mri/empty.s
gas/testsuite/gas/mri/equ.d
gas/testsuite/gas/mri/equ.s
gas/testsuite/gas/mri/expr.d
gas/testsuite/gas/mri/expr.s
gas/testsuite/gas/mri/float.s
gas/testsuite/gas/mri/for.s
gas/testsuite/gas/mri/if.s
gas/testsuite/gas/mri/immconst.d
gas/testsuite/gas/mri/label.d
gas/testsuite/gas/mri/label.s
gas/testsuite/gas/mri/moveml.s
gas/testsuite/gas/mri/repeat.s
gas/testsuite/gas/mri/semi.d
gas/testsuite/gas/mri/semi.s
gas/testsuite/gas/mri/while.s
gas/testsuite/gas/ppc/astest.s
gas/testsuite/gas/sh/fp.s
gas/testsuite/gas/sparc-solaris/addend.s
gas/testsuite/gas/sparc-solaris/sol-cc.s
gas/testsuite/gas/sparc-solaris/sol-gcc.s
gas/testsuite/gas/sparc/asi.d
gas/testsuite/gas/sparc/asi.s
gas/testsuite/gas/sparc/membar.d
gas/testsuite/gas/sparc/membar.s
gas/testsuite/gas/sparc/mism-1.s
gas/testsuite/gas/sparc/prefetch.s
gas/testsuite/gas/sparc/splet-2.d
gas/testsuite/gas/sparc/splet-2.s
gas/testsuite/gas/sparc/splet.d
gas/testsuite/gas/sparc/splet.s
gas/testsuite/gas/sparc/synth.d
gas/testsuite/gas/sparc/synth.s
gas/testsuite/gas/sun4/addend.d
gas/testsuite/gas/sun4/addend.s
gas/testsuite/gas/template
gas/testsuite/gas/v850/arith.s
gas/testsuite/gas/v850/bit.s
gas/testsuite/gas/v850/branch.s
gas/testsuite/gas/v850/compare.s
gas/testsuite/gas/v850/fepsw.s
gas/testsuite/gas/v850/hilo.s
gas/testsuite/gas/v850/hilo2.s
gas/testsuite/gas/v850/jumps.s
gas/testsuite/gas/v850/logical.s
gas/testsuite/gas/v850/mem.s
gas/testsuite/gas/v850/misc.s
gas/testsuite/gas/v850/move.s
gas/testsuite/gas/v850/range.s
gas/testsuite/gas/v850/reloc.s
gas/testsuite/lib/doboth
gas/testsuite/lib/doobjcmp
gas/testsuite/lib/dostriptest
gas/testsuite/lib/dotest
gas/testsuite/lib/dounsreloc
gas/testsuite/lib/dounssym
gprof/.gdbinit
gprof/TEST
gprof/stamp-h.in
include/coff/sym.h
ld/TODO
ld/emulparams/alpha.sh
ld/emulparams/armcoff.sh
ld/emulparams/delta68.sh
ld/emulparams/h8300h.sh
ld/emulparams/h8300s.sh
ld/emulparams/h8500.sh
ld/emulparams/h8500b.sh
ld/emulparams/h8500c.sh
ld/emulparams/h8500m.sh
ld/emulparams/h8500s.sh
ld/emulparams/hp300bsd.sh
ld/emulparams/hp3hpux.sh
ld/emulparams/i386beos.sh
ld/emulparams/i386coff.sh
ld/emulparams/i386nbsd.sh
ld/emulparams/m68kaux.sh
ld/emulparams/news.sh
ld/emulparams/riscix.sh
ld/emulparams/sparcnbsd.sh
ld/emulparams/st2000.sh
ld/emulparams/tic30aout.sh
ld/emulparams/tic30coff.sh
ld/emulparams/w65.sh
ld/emulparams/z8001.sh
ld/emulparams/z8002.sh
ld/scripttempl/aout.sc
ld/scripttempl/i386msdos.sc
ld/scripttempl/i960.sc
ld/scripttempl/m68kcoff.sc
ld/scripttempl/mipsbsd.sc
ld/scripttempl/riscix.sc
ld/scripttempl/st2000.sc
ld/scripttempl/tic30aout.sc
ld/scripttempl/tic30coff.sc
ld/scripttempl/vanilla.sc
ld/stamp-h.in
ld/testsuite/ld-cdtest/cdtest-bar.cc
ld/testsuite/ld-cdtest/cdtest.dat
ld/testsuite/ld-checks/script
ld/testsuite/ld-elfvers/vers13.asym
ld/testsuite/ld-elfvers/vers16.c
ld/testsuite/ld-elfvers/vers16.map
ld/testsuite/ld-elfvers/vers16a.c
ld/testsuite/ld-elfvers/vers2.map
ld/testsuite/ld-elfvers/vers7.map
ld/testsuite/ld-elfvers/vers8.c
ld/testsuite/ld-scripts/cross1.c
ld/testsuite/ld-scripts/cross2.c
ld/testsuite/ld-scripts/cross3.c
ld/testsuite/ld-scripts/defined.t
ld/testsuite/ld-scripts/phdrs.s
ld/testsuite/ld-scripts/script.s
ld/testsuite/ld-scripts/script.t
ld/testsuite/ld-scripts/scriptm.t
ld/testsuite/ld-scripts/sizeof.s
ld/testsuite/ld-scripts/sizeof.t
ld/testsuite/ld-scripts/weak.t
ld/testsuite/ld-selective/1.c
ld/testsuite/ld-selective/2.c
ld/testsuite/ld-sh/sh1.s
ld/testsuite/ld-sh/sh2.c
ld/testsuite/ld-sh/start.s
ld/testsuite/ld-shared/shared.dat
ld/testsuite/ld-shared/sun4.dat
ld/testsuite/ld-shared/xcoff.dat
ld/testsuite/ld-srec/sr1.c
ld/testsuite/ld-srec/sr2.c
ld/testsuite/ld-undefined/undefined.c
ld/testsuite/ld-versados/t1-1.ro
ld/testsuite/ld-versados/t1-2.ro
ld/testsuite/ld-versados/t1.ld
ld/testsuite/ld-versados/t1.ook
ld/testsuite/ld-versados/t2-1.ro
ld/testsuite/ld-versados/t2-2.ro
ld/testsuite/ld-versados/t2-3.ro
ld/testsuite/ld-versados/t2.ld
ld/testsuite/ld-versados/t2.ook
libiberty/config/mh-aix
libiberty/config/mh-cxux7
libiberty/config/mh-fbsd21
libiberty/config/mh-windows
libiberty/msdos.c
makefile.vms
opcodes/stamp-h.in
Delete:
.gitignore
djunpack.bat
gdb/.dir-locals.el
gdb/.gitignore
gdb/CONTRIBUTE
gdb/COPYING
gdb/ChangeLog
gdb/ChangeLog-1990
gdb/ChangeLog-1991
gdb/ChangeLog-1992
gdb/ChangeLog-1993
gdb/ChangeLog-1994
gdb/ChangeLog-1995
gdb/ChangeLog-1996
gdb/ChangeLog-1997
gdb/ChangeLog-1998
gdb/ChangeLog-1999
gdb/ChangeLog-2000
gdb/ChangeLog-2001
gdb/ChangeLog-2002
gdb/ChangeLog-2003
gdb/ChangeLog-2004
gdb/ChangeLog-2005
gdb/ChangeLog-2006
gdb/ChangeLog-2007
gdb/ChangeLog-2008
gdb/ChangeLog-2009
gdb/ChangeLog-2010
gdb/ChangeLog-2011
gdb/ChangeLog-2012
gdb/ChangeLog-3.x
gdb/MAINTAINERS
gdb/Makefile.in
gdb/NEWS
gdb/PROBLEMS
gdb/README
gdb/aarch64-linux-nat.c
gdb/aarch64-linux-tdep.c
gdb/aarch64-linux-tdep.h
gdb/aarch64-newlib-tdep.c
gdb/aarch64-tdep.c
gdb/aarch64-tdep.h
gdb/acinclude.m4
gdb/aclocal.m4
gdb/acx_configure_dir.m4
gdb/ada-exp.y
gdb/ada-lang.c
gdb/ada-lang.h
gdb/ada-lex.l
gdb/ada-operator.def
gdb/ada-tasks.c
gdb/ada-typeprint.c
gdb/ada-valprint.c
gdb/ada-varobj.c
gdb/ada-varobj.h
gdb/addrmap.c
gdb/addrmap.h
gdb/agent.c
gdb/aix-thread.c
gdb/alpha-linux-nat.c
gdb/alpha-linux-tdep.c
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gdb/reggroups.c
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gdb/registry.c
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gdb/remote-fileio.c
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gdb/reply_mig_hack.awk
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gdb/stap-probe.c
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gdb/std-operator.def
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gdb/stubs/ChangeLog
gdb/stubs/buildvms.com
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gdb/stubs/ia64vms-stub.c
gdb/stubs/m32r-stub.c
gdb/stubs/m68k-stub.c
gdb/stubs/sh-stub.c
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gdb/syscalls/amd64-linux.xml
gdb/syscalls/arm-linux.py
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gdb/testsuite/gdb.ada/Makefile.in
gdb/testsuite/gdb.ada/aliased_array.exp
gdb/testsuite/gdb.ada/aliased_array/foo.adb
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gdb/testsuite/gdb.ada/array_bounds/bar.adb
gdb/testsuite/gdb.ada/array_return.exp
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gdb/testsuite/gdb.ada/arrayidx.exp
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gdb/testsuite/gdb.ada/arrayptr.exp
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gdb/testsuite/gdb.ada/fullname_bp.exp
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gdb/testsuite/gdb.ada/gnat_ada.gpr
gdb/testsuite/gdb.ada/homonym.exp
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gdb/testsuite/gdb.ada/info_locals_renaming.exp
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gdb/testsuite/gdb.ada/info_locals_renaming/pck.adb
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gdb/testsuite/gdb.ada/info_types.c
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gdb/testsuite/gdb.ada/int_deref.exp
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gdb/testsuite/gdb.ada/interface.exp
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gdb/testsuite/gdb.ada/iwide.exp
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gdb/testsuite/gdb.ada/lang_switch/lang_switch.adb
gdb/testsuite/gdb.ada/mi_catch_ex.exp
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gdb/testsuite/gdb.ada/mi_task_arg.exp
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gdb/testsuite/gdb.ada/mi_task_info.exp
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gdb/testsuite/gdb.ada/mod_from_name.exp
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gdb/testsuite/gdb.ada/nested.exp
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gdb/testsuite/gdb.ada/null_array.exp
gdb/testsuite/gdb.ada/null_array/foo.adb
gdb/testsuite/gdb.ada/null_array/pck.adb
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gdb/testsuite/gdb.ada/null_record.exp
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gdb/testsuite/gdb.ada/operator_bp.exp
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gdb/testsuite/gdb.ada/packed_array.exp
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gdb/testsuite/gdb.ada/packed_tagged.exp
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gdb/testsuite/gdb.ada/print_chars.exp
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gdb/testsuite/gdb.ada/ptype_tagged_param/pck.adb
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gdb/testsuite/gdb.ada/rdv_wait.exp
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gdb/testsuite/gdb.ada/rec_return.exp
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gdb/testsuite/gdb.ada/ref_param.exp
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gdb/testsuite/gdb.ada/ref_tick_size.exp
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gdb/testsuite/gdb.ada/same_enum.exp
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gdb/testsuite/gdb.ada/set_pckd_arr_elt.exp
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gdb/testsuite/gdb.ada/start.exp
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gdb/testsuite/gdb.ada/sym_print_name.exp
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gdb/testsuite/gdb.ada/taft_type.exp
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gdb/testsuite/gdb.ada/task_bp.exp
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gdb/testsuite/gdb.ada/type_coercion.exp
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gdb/testsuite/gdb.ada/unc_arr_ptr_in_var_rec.exp
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gdb/testsuite/gdb.ada/variant_record_packed_array.exp
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gdb/testsuite/gdb.asm/Makefile.in
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gdb/testsuite/gdb.base/arrayidx.c
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gdb/testsuite/gdb.base/async-shell.c
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gdb/testsuite/gdb.base/baz.c
gdb/testsuite/gdb.base/bfp-test.c
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gdb/testsuite/gdb.base/bigcore.c
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gdb/testsuite/gdb.base/bitfields2.c
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gdb/testsuite/gdb.base/comp-dir/subdir/dummy.txt
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gdb/testsuite/gdb.base/del.c
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sim/testsuite/sim/sh64/media/bgt.cgs
sim/testsuite/sim/sh64/media/bgtu.cgs
sim/testsuite/sim/sh64/media/blink.cgs
sim/testsuite/sim/sh64/media/bne.cgs
sim/testsuite/sim/sh64/media/bnei.cgs
sim/testsuite/sim/sh64/media/brk.cgs
sim/testsuite/sim/sh64/media/byterev.cgs
sim/testsuite/sim/sh64/media/cmpeq.cgs
sim/testsuite/sim/sh64/media/cmpgt.cgs
sim/testsuite/sim/sh64/media/cmpgtu.cgs
sim/testsuite/sim/sh64/media/cmveq.cgs
sim/testsuite/sim/sh64/media/cmvne.cgs
sim/testsuite/sim/sh64/media/fabsd.cgs
sim/testsuite/sim/sh64/media/fabss.cgs
sim/testsuite/sim/sh64/media/faddd.cgs
sim/testsuite/sim/sh64/media/fadds.cgs
sim/testsuite/sim/sh64/media/fcmpeqd.cgs
sim/testsuite/sim/sh64/media/fcmpeqs.cgs
sim/testsuite/sim/sh64/media/fcmpged.cgs
sim/testsuite/sim/sh64/media/fcmpges.cgs
sim/testsuite/sim/sh64/media/fcmpgtd.cgs
sim/testsuite/sim/sh64/media/fcmpgts.cgs
sim/testsuite/sim/sh64/media/fcmpund.cgs
sim/testsuite/sim/sh64/media/fcmpuns.cgs
sim/testsuite/sim/sh64/media/fcnvds.cgs
sim/testsuite/sim/sh64/media/fcnvsd.cgs
sim/testsuite/sim/sh64/media/fdivd.cgs
sim/testsuite/sim/sh64/media/fdivs.cgs
sim/testsuite/sim/sh64/media/fgetscr.cgs
sim/testsuite/sim/sh64/media/fiprs.cgs
sim/testsuite/sim/sh64/media/fldd.cgs
sim/testsuite/sim/sh64/media/fldp.cgs
sim/testsuite/sim/sh64/media/flds.cgs
sim/testsuite/sim/sh64/media/fldxd.cgs
sim/testsuite/sim/sh64/media/fldxp.cgs
sim/testsuite/sim/sh64/media/fldxs.cgs
sim/testsuite/sim/sh64/media/floatld.cgs
sim/testsuite/sim/sh64/media/floatls.cgs
sim/testsuite/sim/sh64/media/floatqd.cgs
sim/testsuite/sim/sh64/media/floatqs.cgs
sim/testsuite/sim/sh64/media/fmacs.cgs
sim/testsuite/sim/sh64/media/fmovd.cgs
sim/testsuite/sim/sh64/media/fmovdq.cgs
sim/testsuite/sim/sh64/media/fmovls.cgs
sim/testsuite/sim/sh64/media/fmovqd.cgs
sim/testsuite/sim/sh64/media/fmovs.cgs
sim/testsuite/sim/sh64/media/fmovsl.cgs
sim/testsuite/sim/sh64/media/fmuld.cgs
sim/testsuite/sim/sh64/media/fmuls.cgs
sim/testsuite/sim/sh64/media/fnegd.cgs
sim/testsuite/sim/sh64/media/fnegs.cgs
sim/testsuite/sim/sh64/media/fputscr.cgs
sim/testsuite/sim/sh64/media/fsqrtd.cgs
sim/testsuite/sim/sh64/media/fsqrts.cgs
sim/testsuite/sim/sh64/media/fstd.cgs
sim/testsuite/sim/sh64/media/fstp.cgs
sim/testsuite/sim/sh64/media/fsts.cgs
sim/testsuite/sim/sh64/media/fstxd.cgs
sim/testsuite/sim/sh64/media/fstxp.cgs
sim/testsuite/sim/sh64/media/fstxs.cgs
sim/testsuite/sim/sh64/media/fsubd.cgs
sim/testsuite/sim/sh64/media/fsubs.cgs
sim/testsuite/sim/sh64/media/ftrcdl.cgs
sim/testsuite/sim/sh64/media/ftrcdq.cgs
sim/testsuite/sim/sh64/media/ftrcsl.cgs
sim/testsuite/sim/sh64/media/ftrcsq.cgs
sim/testsuite/sim/sh64/media/ftrvs.cgs
sim/testsuite/sim/sh64/media/getcfg.cgs
sim/testsuite/sim/sh64/media/getcon.cgs
sim/testsuite/sim/sh64/media/gettr.cgs
sim/testsuite/sim/sh64/media/icbi.cgs
sim/testsuite/sim/sh64/media/ldb.cgs
sim/testsuite/sim/sh64/media/ldhil.cgs
sim/testsuite/sim/sh64/media/ldhiq.cgs
sim/testsuite/sim/sh64/media/ldl.cgs
sim/testsuite/sim/sh64/media/ldlol.cgs
sim/testsuite/sim/sh64/media/ldloq.cgs
sim/testsuite/sim/sh64/media/ldq.cgs
sim/testsuite/sim/sh64/media/ldub.cgs
sim/testsuite/sim/sh64/media/lduw.cgs
sim/testsuite/sim/sh64/media/ldw.cgs
sim/testsuite/sim/sh64/media/ldxb.cgs
sim/testsuite/sim/sh64/media/ldxl.cgs
sim/testsuite/sim/sh64/media/ldxq.cgs
sim/testsuite/sim/sh64/media/ldxub.cgs
sim/testsuite/sim/sh64/media/ldxuw.cgs
sim/testsuite/sim/sh64/media/ldxw.cgs
sim/testsuite/sim/sh64/media/mabsl.cgs
sim/testsuite/sim/sh64/media/mabsw.cgs
sim/testsuite/sim/sh64/media/maddl.cgs
sim/testsuite/sim/sh64/media/maddsl.cgs
sim/testsuite/sim/sh64/media/maddsub.cgs
sim/testsuite/sim/sh64/media/maddsw.cgs
sim/testsuite/sim/sh64/media/maddw.cgs
sim/testsuite/sim/sh64/media/mcmpeqb.cgs
sim/testsuite/sim/sh64/media/mcmpeql.cgs
sim/testsuite/sim/sh64/media/mcmpeqw.cgs
sim/testsuite/sim/sh64/media/mcmpgtl.cgs
sim/testsuite/sim/sh64/media/mcmpgtub.cgs
sim/testsuite/sim/sh64/media/mcmpgtw.cgs
sim/testsuite/sim/sh64/media/mcmv.cgs
sim/testsuite/sim/sh64/media/mcnvslw.cgs
sim/testsuite/sim/sh64/media/mcnvswb.cgs
sim/testsuite/sim/sh64/media/mcnvswub.cgs
sim/testsuite/sim/sh64/media/mextr1.cgs
sim/testsuite/sim/sh64/media/mextr2.cgs
sim/testsuite/sim/sh64/media/mextr3.cgs
sim/testsuite/sim/sh64/media/mextr4.cgs
sim/testsuite/sim/sh64/media/mextr5.cgs
sim/testsuite/sim/sh64/media/mextr6.cgs
sim/testsuite/sim/sh64/media/mextr7.cgs
sim/testsuite/sim/sh64/media/mmacfxwl.cgs
sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs
sim/testsuite/sim/sh64/media/mmulfxl.cgs
sim/testsuite/sim/sh64/media/mmulfxrpw.cgs
sim/testsuite/sim/sh64/media/mmulfxw.cgs
sim/testsuite/sim/sh64/media/mmulhiwl.cgs
sim/testsuite/sim/sh64/media/mmull.cgs
sim/testsuite/sim/sh64/media/mmullowl.cgs
sim/testsuite/sim/sh64/media/mmulsumwq.cgs
sim/testsuite/sim/sh64/media/mmulw.cgs
sim/testsuite/sim/sh64/media/movi.cgs
sim/testsuite/sim/sh64/media/mpermw.cgs
sim/testsuite/sim/sh64/media/msadubq.cgs
sim/testsuite/sim/sh64/media/mshaldsl.cgs
sim/testsuite/sim/sh64/media/mshaldsw.cgs
sim/testsuite/sim/sh64/media/mshardl.cgs
sim/testsuite/sim/sh64/media/mshardsq.cgs
sim/testsuite/sim/sh64/media/mshardw.cgs
sim/testsuite/sim/sh64/media/mshfhib.cgs
sim/testsuite/sim/sh64/media/mshfhil.cgs
sim/testsuite/sim/sh64/media/mshfhiw.cgs
sim/testsuite/sim/sh64/media/mshflob.cgs
sim/testsuite/sim/sh64/media/mshflol.cgs
sim/testsuite/sim/sh64/media/mshflow.cgs
sim/testsuite/sim/sh64/media/mshlldl.cgs
sim/testsuite/sim/sh64/media/mshlldw.cgs
sim/testsuite/sim/sh64/media/mshlrdl.cgs
sim/testsuite/sim/sh64/media/mshlrdw.cgs
sim/testsuite/sim/sh64/media/msubl.cgs
sim/testsuite/sim/sh64/media/msubsl.cgs
sim/testsuite/sim/sh64/media/msubsub.cgs
sim/testsuite/sim/sh64/media/msubsw.cgs
sim/testsuite/sim/sh64/media/msubw.cgs
sim/testsuite/sim/sh64/media/mulsl.cgs
sim/testsuite/sim/sh64/media/mulul.cgs
sim/testsuite/sim/sh64/media/nop.cgs
sim/testsuite/sim/sh64/media/nsb.cgs
sim/testsuite/sim/sh64/media/ocbi.cgs
sim/testsuite/sim/sh64/media/ocbp.cgs
sim/testsuite/sim/sh64/media/ocbwb.cgs
sim/testsuite/sim/sh64/media/or.cgs
sim/testsuite/sim/sh64/media/ori.cgs
sim/testsuite/sim/sh64/media/prefi.cgs
sim/testsuite/sim/sh64/media/pta.cgs
sim/testsuite/sim/sh64/media/ptabs.cgs
sim/testsuite/sim/sh64/media/ptb.cgs
sim/testsuite/sim/sh64/media/ptrel.cgs
sim/testsuite/sim/sh64/media/putcfg.cgs
sim/testsuite/sim/sh64/media/putcon.cgs
sim/testsuite/sim/sh64/media/rte.cgs
sim/testsuite/sim/sh64/media/shard.cgs
sim/testsuite/sim/sh64/media/shardl.cgs
sim/testsuite/sim/sh64/media/shari.cgs
sim/testsuite/sim/sh64/media/sharil.cgs
sim/testsuite/sim/sh64/media/shlld.cgs
sim/testsuite/sim/sh64/media/shlldl.cgs
sim/testsuite/sim/sh64/media/shlli.cgs
sim/testsuite/sim/sh64/media/shllil.cgs
sim/testsuite/sim/sh64/media/shlrd.cgs
sim/testsuite/sim/sh64/media/shlrdl.cgs
sim/testsuite/sim/sh64/media/shlri.cgs
sim/testsuite/sim/sh64/media/shlril.cgs
sim/testsuite/sim/sh64/media/shori.cgs
sim/testsuite/sim/sh64/media/sleep.cgs
sim/testsuite/sim/sh64/media/stb.cgs
sim/testsuite/sim/sh64/media/sthil.cgs
sim/testsuite/sim/sh64/media/sthiq.cgs
sim/testsuite/sim/sh64/media/stl.cgs
sim/testsuite/sim/sh64/media/stlol.cgs
sim/testsuite/sim/sh64/media/stloq.cgs
sim/testsuite/sim/sh64/media/stq.cgs
sim/testsuite/sim/sh64/media/stw.cgs
sim/testsuite/sim/sh64/media/stxb.cgs
sim/testsuite/sim/sh64/media/stxl.cgs
sim/testsuite/sim/sh64/media/stxq.cgs
sim/testsuite/sim/sh64/media/stxw.cgs
sim/testsuite/sim/sh64/media/sub.cgs
sim/testsuite/sim/sh64/media/subl.cgs
sim/testsuite/sim/sh64/media/swapq.cgs
sim/testsuite/sim/sh64/media/synci.cgs
sim/testsuite/sim/sh64/media/synco.cgs
sim/testsuite/sim/sh64/media/testutils.inc
sim/testsuite/sim/sh64/media/trapa.cgs
sim/testsuite/sim/sh64/media/xor.cgs
sim/testsuite/sim/sh64/media/xori.cgs
sim/testsuite/sim/sh64/misc/fr-dr.s
sim/testsuite/sim/v850/ChangeLog
sim/testsuite/sim/v850/allinsns.exp
sim/testsuite/sim/v850/bsh.cgs
sim/testsuite/sim/v850/div.cgs
sim/testsuite/sim/v850/divh.cgs
sim/testsuite/sim/v850/divh_3.cgs
sim/testsuite/sim/v850/divhu.cgs
sim/testsuite/sim/v850/divu.cgs
sim/testsuite/sim/v850/sar.cgs
sim/testsuite/sim/v850/satadd.cgs
sim/testsuite/sim/v850/satsub.cgs
sim/testsuite/sim/v850/satsubi.cgs
sim/testsuite/sim/v850/satsubr.cgs
sim/testsuite/sim/v850/shl.cgs
sim/testsuite/sim/v850/shr.cgs
sim/testsuite/sim/v850/testutils.cgs
sim/testsuite/sim/v850/testutils.inc
sim/v850/ChangeLog
sim/v850/Makefile.in
sim/v850/aclocal.m4
sim/v850/config.in
sim/v850/configure
sim/v850/configure.ac
sim/v850/interp.c
sim/v850/sim-main.h
sim/v850/simops.c
sim/v850/simops.h
sim/v850/v850-dc
sim/v850/v850.igen
sim/v850/v850_sim.h
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* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
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* mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
(sc, swxc1): Likewise. Also fix big-endian and reverse-endian
shifts for that case.
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CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
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and mips64.
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* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
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jumps with hazard barrier.
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uninterpreted formats. If fmt is one of the uninterpreted types
don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
fmt_word, and fmt_uninterpreted_64 like fmt_long.
(store_fpr): When writing an invalid odd register, set the
matching even register to fmt_unknown, not the following register.
* interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
the the memory window at offset 0 set by --memory-size command
line option.
(sim_store_register): Handle storing 4 bytes to an 8 byte floating
point register.
(sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
register.
(sim_monitor): When returning the memory size to the MIPS
application, use the value in STATE_MEM_SIZE, not an arbitrary
hardcoded value.
(cop_lw): Don' mess around with FPR_STATE, just pass
fmt_uninterpreted_32 to StoreFPR.
(cop_sw): Similarly.
(cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
(cop_sd): Similarly.
* mips.igen (not_word_value): Single version for mips32, mips64
and mips16.
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sim_igen_machine.
* configure: Regenerate.
* mips.igen (model): Add smartmips.
(MADDU): Increment ACX if carry.
(do_mult): Clear ACX.
(ROR,RORV): Add smartmips.
(include): Include smartmips.igen.
* sim-main.h (ACX): Set to REGISTERS[89].
* smartmips.igen: New file.
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(dsp.o): New dependency.
(IGEN_INCLUDE): Add dsp.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
mipsisa64*-*-*): Add dsp to sim_igen_machine.
* configure: Regenerate.
* mips.igen: Add dsp model and include dsp.igen.
(MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
because these instructions are extended in DSP ASE.
* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
adding 6 DSP accumulator registers and 1 DSP control register.
(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
DSPCR_CCOND_SMASK): New define.
(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
* dsp.c, dsp.igen: New files for MIPS DSP ASE.
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(check_u64): Add mips16e tag.
* m16e.igen: New file for MIPS16e instructions.
* configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
models.
* configure: Regenerate.
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* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
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* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
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(MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
* mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
separate implementations for mipsIV and mipsV. Use new macros to
determine whether the restrictions apply.
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* mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
(check_mult_hilo): Improve comments.
(check_div_hilo): Likewise. Also, fork off a new version
to handle mips32/mips64 (since there are no hazards to check
in MIPS32/MIPS64).
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* mips.igen (do_dmultx): Fix check for negative operands.
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* mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
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* mips.igen (EI, DI): Remove.
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Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
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* sim-main.h (check_branch_bug, mark_branch_bug): Remove.
* mips.igen: Remove all invocations of check_branch_bug and
mark_branch_bug.
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* mips.igen (do_load_double, do_store_double): New functions.
(LDC1, SDC1): Rename to...
(LDC1b, SDC1b): respectively.
(LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
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Ed Satterthwaite <ehs@broadcom.com>
* mips3d.igen: New file which contains MIPS-3D ASE instructions.
* Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
* mips.igen: Include mips3d.igen.
(mips3d): New model name for MIPS-3D ASE instructions.
(CVT.W.fmt): Don't use this instruction for word (source) format
instructions.
* cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
(fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
(fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
(NR_FRAC_GUARD, IMPLICIT_1): New macros.
* sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
(RSquareRoot1, RSquareRoot2): New macros.
(fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
(fp_rsqrt2): New functions.
* configure.in: Add MIPS-3D support to mipsisa64 simulator.
* configure: Regenerate.
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* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
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* mips.igen: Fix formatting of function calls in
many FP operations.
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* mips.igen (MOVN, MOVZ): Trace result.
(TNEI): Print "tnei" as the opcode name in traces.
(CEIL.W): Add disassembly string for traces.
(RSQRT.fmt): Make location of disassembly string consistent
with other instructions.
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* mips.igen (X): Delete unused function.
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Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
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Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
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* sim-main.h (FGRIDX): Remove, replace all uses with...
(FGR_BASE): New macro.
(FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
(_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
(NR_FGR, FGR): Likewise.
* interp.c: Replace all uses of FGRIDX with FGR_BASE.
* mips.igen: Likewise.
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Ed Satterthwaite <ehs@broadcom.com>
* configure.in (mipsisa64sb1*-*-*): New target for supporting
Broadcom SiByte SB-1 processor configurations.
* configure: Regenerate.
* sb1.igen: New file.
* mips.igen: Include sb1.igen.
(sb1): New model.
* Makefile.in (IGEN_INCLUDE): Add sb1.igen.
* mdmx.igen: Add "sb1" model to all appropriate functions and
instructions.
* mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
(ob_func, ob_acc): Reference the above.
(qh_acc): Adjust to keep the same size as ob_acc.
* sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
(MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
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Ed Satterthwaite <ehs@broadcom.com>
* mips.igen (mdmx): New (pseudo-)model.
* mdmx.c, mdmx.igen: New files.
* Makefile.in (SIM_OBJS): Add mdmx.o.
* sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
New typedefs.
(ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
(MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
(MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
(MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
(MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
(MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
(MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
(MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
(MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
(MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
(MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
(MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
(SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
(qh_fmtsel): New macros.
(_sim_cpu): New member "acc".
(mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
(mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
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* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
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* mips.igen: Fix formatting of calls to Unpredictable().
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* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
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* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
immediate or code as a hex value with the "%#lx" format.
(ANDI): Likewise, and fix printed instruction name.
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* mips.igen (check_fpu): Enable check for coprocessor 1 usability.
* sim-main.h (COP_Usable): Define, but for now coprocessor 1
is always enabled.
(SignalExceptionCoProcessorUnusable): Take as argument the
unusable coprocessor number.
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* mips.igen: Fix formatting of all SignalException calls.
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* mips.igen: Remove gencode comment from top of file, fix
spelling in another comment.
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* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
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* mips.igen: Fix formatting of check_fpu calls.
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* mips.igen (FLOOR.L.fmt): Store correct destination register.
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* mips.igen: Remove whitespace at end of lines.
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* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
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* interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
* mips.igen (LL, CxC1, MxC1): Likewise.
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* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
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* mips.igen (do_divu): Fix spacing.
* mips.igen (do_dsllv): Move to be right before DSLLV,
to match the rest of the do_<shift> functions.
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* mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
DSRL32, do_dsrlv): Trace inputs and results.
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* mips.igen (CACHE): Provide instruction-printing string.
* interp.c (signal_exception): Comment tokens after #endif.
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* mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
(MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
LWC1, SWC1): Add "f" to filter, since these are FP instructions.
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* mips.igen (DSRA32, DSRAV): Fix order of arguments in
instruction-printing string.
(LWU): Use '64' as the filter flag.
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