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* sim: bfin: tweak saturation handling with TFU/FU modes and MM bitMike Frysinger2011-06-182-14/+35
* sim: bfin: handle large shift values with accumulator shift insnsMike Frysinger2011-06-182-2/+14
* sim: bfin: handle odd shift values with shift insnsMike Frysinger2011-06-182-7/+36
* sim: bfin: fix M_IH saturation sizeMike Frysinger2011-06-182-17/+6
* sim: bfin: handle V/VS saturation in dsp mac insnsMike Frysinger2011-06-182-25/+58
* sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insnsMike Frysinger2011-06-182-0/+10
* sim: bfin: fix sign extension in dsp insns with MM flagMike Frysinger2011-06-182-8/+10
* sim: bfin: fix dsp insns IH saturation/rounding behaviorMike Frysinger2011-06-182-1/+16
* sim: bfin: fix inverted changelog entryMike Frysinger2011-06-181-1/+1
* sim: bfin: fix accumulator edge case saturationMike Frysinger2011-06-182-2/+7
* sim: bfin: use freeargv for freeing argvsMike Frysinger2011-06-182-1/+5
* sim: bfin: add support for glued SIC interrupt linesMike Frysinger2011-06-042-25/+71
* sim: bfin: push SIC mappings to device treeMike Frysinger2011-06-043-589/+723
* sim: bfin: dma: fix indentationMike Frysinger2011-06-032-1/+5
* sim: bfin: switch to new syscall trace levelMike Frysinger2011-05-262-1/+5
* sim: bfin: move model data into machs.hMike Frysinger2011-05-2531-109/+80
* sim: bfin: add a performance monitor stubMike Frysinger2011-05-257-0/+196
* sim: bfin: add bf526-0.2/bf54x-0.4 rom regionsMike Frysinger2011-05-256-0/+27
* sim: bfin: allow pushing of SPMike Frysinger2011-05-142-2/+6
* sim: bfin: implement loop back support in the UARTsMike Frysinger2011-05-144-23/+62
* sim: bfin: fix UART LSR read-only bit saturationMike Frysinger2011-05-092-0/+6
* sim: bfin: constify dmac pmap arraysMike Frysinger2011-04-272-13/+22
* sim: gpio: add output supportMike Frysinger2011-04-262-16/+53
* sim: gpio: update mask a/b signals betterMike Frysinger2011-04-262-12/+49
* sim: bfin: use store buffer with more 32bit insnsMike Frysinger2011-04-162-23/+37
* sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger2011-04-152-0/+30
* sim: bfin: respect the port level on signals to the SICMike Frysinger2011-04-112-16/+32
* sim: bfin: add missing GPIO pin 15Mike Frysinger2011-04-112-0/+5
* sim: bfin: add OTP output portMike Frysinger2011-04-012-0/+12
* sim: bfin: regen configure to include new cfi deviceMike Frysinger2011-03-292-1/+5
* sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger2011-03-292-9/+9
* sim: bfin: handle saturation with RND12 sub insnsMike Frysinger2011-03-272-1/+11
* sim: bfin: add missing VS set with add/sub insnsMike Frysinger2011-03-262-0/+7
* sim: bfin: add hw tracing to gpio/sic port eventsMike Frysinger2011-03-253-10/+64
* sim: bfin: fix GPIO logic bugs when processing eventsMike Frysinger2011-03-252-4/+16
* sim: bfin: fix clear/set/toggle GPIO handlingMike Frysinger2011-03-252-0/+11
* sim: bfin: document SIC limitationMike Frysinger2011-03-242-1/+27
* sim: bfin: fix inverted W1C logicMike Frysinger2011-03-2414-17/+34
* sim: bfin: define more UART LSR bitsMike Frysinger2011-03-242-7/+16
* sim: bfin: fix typo in TWI stat regMike Frysinger2011-03-242-1/+5
* sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger2011-03-242-2/+7
* sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger2011-03-242-0/+10
* sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger2011-03-242-6/+14
* sim: bfin: fix thinko in SIC pin encodingMike Frysinger2011-03-242-511/+516
* sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger2011-03-242-9/+5
* sim: bfin: fix thinko in bfin_gpio bus addressesMike Frysinger2011-03-242-30/+38
* sim: bfin: check for kill/preadMike Frysinger2011-03-175-2/+25
* sim: bfin: add GPIO device simulationMike Frysinger2011-03-157-28/+369
* sim: bfin: fix brace styleMike Frysinger2011-03-1527-27/+54
* sim: bfin: fix brace styleMike Frysinger2011-03-1558-161/+342
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