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* This commit was manufactured by cvs2svn to create branch 'binutils-nobody2013-09-181-6460/+0
* sim: bfin: note missing parallel handling of SEARCHMike Frysinger2013-06-241-0/+13
* sim: bfin: handle invalid HLs encoding in dsp shift insnsMike Frysinger2013-06-241-5/+9
* sim: bfin: stricter insn decodingMike Frysinger2013-06-191-50/+81
* Update years in copyright notice for the GDB files.Joel Brobecker2013-01-011-1/+1
* sim: bfin: fix ASTAT issues in immediate shiftsMike Frysinger2012-04-091-17/+58
* sim: bfin: fix ASTAT/correctness issues with arithmetic shiftsMike Frysinger2012-04-091-10/+60
* sim: bfin: more parallel insn checksMike Frysinger2012-04-091-18/+66
* sim: bfin: keep track of the exact position of parallel insnsMike Frysinger2012-04-091-44/+49
* sim: bfin: drop excess space in negation insnMike Frysinger2012-04-081-1/+1
* sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slotsMike Frysinger2012-04-011-0/+3
* sim: bfin: simplify field width processing and fix build warningsMike Frysinger2012-04-011-10/+1
* sim: bfin: fix corner case Logical shift issuesMike Frysinger2012-03-191-45/+53
* Copyright year update in most files of the GDB Project.Joel Brobecker2012-01-041-1/+1
* sim: bfin: use store buffer for VIT_MAX insnsMike Frysinger2011-09-291-2/+2
* sim: bfin: set ASTAT AV/AVS when shifting accumulators overflowMike Frysinger2011-06-181-0/+6
* sim: bfin: do not touch ASTAT[V] when shifting accumulatorsMike Frysinger2011-06-181-3/+4
* sim: bfin: do not extend accumulator in LSHIFT insnsMike Frysinger2011-06-181-1/+1
* sim: bfin: tweak saturation handling with TFU/FU modes and MM bitMike Frysinger2011-06-181-14/+30
* sim: bfin: handle large shift values with accumulator shift insnsMike Frysinger2011-06-181-2/+8
* sim: bfin: handle odd shift values with shift insnsMike Frysinger2011-06-181-7/+29
* sim: bfin: fix M_IH saturation sizeMike Frysinger2011-06-181-12/+1
* sim: bfin: handle V/VS saturation in dsp mac insnsMike Frysinger2011-06-181-25/+48
* sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insnsMike Frysinger2011-06-181-0/+4
* sim: bfin: fix sign extension in dsp insns with MM flagMike Frysinger2011-06-181-8/+3
* sim: bfin: fix dsp insns IH saturation/rounding behaviorMike Frysinger2011-06-181-1/+11
* sim: bfin: fix accumulator edge case saturationMike Frysinger2011-06-181-2/+2
* sim: bfin: allow pushing of SPMike Frysinger2011-05-141-2/+1
* sim: bfin: use store buffer with more 32bit insnsMike Frysinger2011-04-161-23/+29
* sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger2011-04-151-0/+24
* sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger2011-03-291-9/+2
* sim: bfin: handle saturation with RND12 sub insnsMike Frysinger2011-03-271-1/+6
* sim: bfin: add missing VS set with add/sub insnsMike Frysinger2011-03-261-0/+3
* sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger2011-03-241-2/+2
* sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger2011-03-241-0/+5
* sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger2011-03-241-6/+8
* sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger2011-03-241-9/+0
* sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger2011-03-151-1/+1
* sim: bfin: skip acc/ASTAT updates for movesMike Frysinger2011-03-151-6/+6
* sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger2011-03-151-8/+33
* sim: bfin: handle V overflows in dsp mult insnsMike Frysinger2011-03-151-7/+9
* sim: bfin: decode ASTAT on failureMike Frysinger2011-03-151-34/+72
* sim: bfin: handle saturation with fract multiplicationsMike Frysinger2011-03-151-0/+2
* sim: bfin: new portMike Frysinger2011-03-061-0/+6099
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