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* sim: bfin: allow pushing of SPMike Frysinger2011-05-141-0/+5
* sim: bfin: implement loop back support in the UARTsMike Frysinger2011-05-141-0/+15
* sim: bfin: fix UART LSR read-only bit saturationMike Frysinger2011-05-091-0/+5
* sim: bfin: constify dmac pmap arraysMike Frysinger2011-04-271-0/+9
* sim: gpio: add output supportMike Frysinger2011-04-261-0/+8
* sim: gpio: update mask a/b signals betterMike Frysinger2011-04-261-0/+12
* sim: bfin: use store buffer with more 32bit insnsMike Frysinger2011-04-161-0/+8
* sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger2011-04-151-0/+6
* sim: bfin: respect the port level on signals to the SICMike Frysinger2011-04-111-0/+7
* sim: bfin: add missing GPIO pin 15Mike Frysinger2011-04-111-0/+4
* sim: bfin: add OTP output portMike Frysinger2011-04-011-0/+5
* sim: bfin: regen configure to include new cfi deviceMike Frysinger2011-03-291-0/+4
* sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger2011-03-291-0/+7
* sim: bfin: handle saturation with RND12 sub insnsMike Frysinger2011-03-271-0/+5
* sim: bfin: add missing VS set with add/sub insnsMike Frysinger2011-03-261-0/+4
* sim: bfin: add hw tracing to gpio/sic port eventsMike Frysinger2011-03-251-0/+10
* sim: bfin: fix GPIO logic bugs when processing eventsMike Frysinger2011-03-251-0/+6
* sim: bfin: fix clear/set/toggle GPIO handlingMike Frysinger2011-03-251-0/+5
* sim: bfin: document SIC limitationMike Frysinger2011-03-241-0/+4
* sim: bfin: fix inverted W1C logicMike Frysinger2011-03-241-0/+17
* sim: bfin: define more UART LSR bitsMike Frysinger2011-03-241-0/+4
* sim: bfin: fix typo in TWI stat regMike Frysinger2011-03-241-0/+4
* sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger2011-03-241-0/+5
* sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger2011-03-241-0/+5
* sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger2011-03-241-0/+6
* sim: bfin: fix thinko in SIC pin encodingMike Frysinger2011-03-241-0/+14
* sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger2011-03-241-0/+5
* sim: bfin: fix thinko in bfin_gpio bus addressesMike Frysinger2011-03-241-0/+7
* sim: bfin: check for kill/preadMike Frysinger2011-03-171-0/+8
* sim: bfin: add GPIO device simulationMike Frysinger2011-03-151-0/+15
* sim: bfin: fix brace styleMike Frysinger2011-03-151-0/+20
* sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger2011-03-151-0/+5
* sim: bfin: skip acc/ASTAT updates for movesMike Frysinger2011-03-151-0/+4
* sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger2011-03-151-0/+7
* sim: bfin: handle V overflows in dsp mult insnsMike Frysinger2011-03-151-0/+6
* sim: bfin: decode ASTAT on failureMike Frysinger2011-03-151-0/+7
* sim: bfin: handle saturation with fract multiplicationsMike Frysinger2011-03-151-0/+4
* sim: bfin: forgot to cvs add the changelogMike Frysinger2011-03-141-0/+29
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