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ppe42-binutils
binutils-2_24-ppe42
GNU Binutils for the PPE42
Raptor Computing Systems
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bfin
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ChangeLog
Commit message (
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Author
Age
Files
Lines
*
sim: bfin: allow pushing of SP
Mike Frysinger
2011-05-14
1
-0
/
+5
*
sim: bfin: implement loop back support in the UARTs
Mike Frysinger
2011-05-14
1
-0
/
+15
*
sim: bfin: fix UART LSR read-only bit saturation
Mike Frysinger
2011-05-09
1
-0
/
+5
*
sim: bfin: constify dmac pmap arrays
Mike Frysinger
2011-04-27
1
-0
/
+9
*
sim: gpio: add output support
Mike Frysinger
2011-04-26
1
-0
/
+8
*
sim: gpio: update mask a/b signals better
Mike Frysinger
2011-04-26
1
-0
/
+12
*
sim: bfin: use store buffer with more 32bit insns
Mike Frysinger
2011-04-16
1
-0
/
+8
*
sim: bfin: handle implicit DISALGNEXCPT with video insns
Mike Frysinger
2011-04-15
1
-0
/
+6
*
sim: bfin: respect the port level on signals to the SIC
Mike Frysinger
2011-04-11
1
-0
/
+7
*
sim: bfin: add missing GPIO pin 15
Mike Frysinger
2011-04-11
1
-0
/
+4
*
sim: bfin: add OTP output port
Mike Frysinger
2011-04-01
1
-0
/
+5
*
sim: bfin: regen configure to include new cfi device
Mike Frysinger
2011-03-29
1
-0
/
+4
*
sim: bfin: fix sign extension with 16bit acc add insns
Mike Frysinger
2011-03-29
1
-0
/
+7
*
sim: bfin: handle saturation with RND12 sub insns
Mike Frysinger
2011-03-27
1
-0
/
+5
*
sim: bfin: add missing VS set with add/sub insns
Mike Frysinger
2011-03-26
1
-0
/
+4
*
sim: bfin: add hw tracing to gpio/sic port events
Mike Frysinger
2011-03-25
1
-0
/
+10
*
sim: bfin: fix GPIO logic bugs when processing events
Mike Frysinger
2011-03-25
1
-0
/
+6
*
sim: bfin: fix clear/set/toggle GPIO handling
Mike Frysinger
2011-03-25
1
-0
/
+5
*
sim: bfin: document SIC limitation
Mike Frysinger
2011-03-24
1
-0
/
+4
*
sim: bfin: fix inverted W1C logic
Mike Frysinger
2011-03-24
1
-0
/
+17
*
sim: bfin: define more UART LSR bits
Mike Frysinger
2011-03-24
1
-0
/
+4
*
sim: bfin: fix typo in TWI stat reg
Mike Frysinger
2011-03-24
1
-0
/
+4
*
sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set
Mike Frysinger
2011-03-24
1
-0
/
+5
*
sim: bfin: always do 16bit sign extension with the SEARCH insn
Mike Frysinger
2011-03-24
1
-0
/
+5
*
sim: bfin: update AV and AC ASTAT bits with acc negation
Mike Frysinger
2011-03-24
1
-0
/
+6
*
sim: bfin: fix thinko in SIC pin encoding
Mike Frysinger
2011-03-24
1
-0
/
+14
*
sim: bfin: allow byteop[123]p src regs to be the same
Mike Frysinger
2011-03-24
1
-0
/
+5
*
sim: bfin: fix thinko in bfin_gpio bus addresses
Mike Frysinger
2011-03-24
1
-0
/
+7
*
sim: bfin: check for kill/pread
Mike Frysinger
2011-03-17
1
-0
/
+8
*
sim: bfin: add GPIO device simulation
Mike Frysinger
2011-03-15
1
-0
/
+15
*
sim: bfin: fix brace style
Mike Frysinger
2011-03-15
1
-0
/
+20
*
sim: bfin: handle AZ updates with 16bit adds/subs
Mike Frysinger
2011-03-15
1
-0
/
+5
*
sim: bfin: skip acc/ASTAT updates for moves
Mike Frysinger
2011-03-15
1
-0
/
+4
*
sim: bfin: handle AN (negative overflows) in dsp mult insns
Mike Frysinger
2011-03-15
1
-0
/
+7
*
sim: bfin: handle V overflows in dsp mult insns
Mike Frysinger
2011-03-15
1
-0
/
+6
*
sim: bfin: decode ASTAT on failure
Mike Frysinger
2011-03-15
1
-0
/
+7
*
sim: bfin: handle saturation with fract multiplications
Mike Frysinger
2011-03-15
1
-0
/
+4
*
sim: bfin: forgot to cvs add the changelog
Mike Frysinger
2011-03-14
1
-0
/
+29