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* * mips-dis.c (print_insn_arg): Print condition code registers asIan Lance Taylor1996-09-092-31/+85
* * v850-dis.c (disassemble): Make static. Provide prototype.Jeff Law1996-09-031-0/+9
* whoops--typoIan Lance Taylor1996-09-021-0/+27
* file was really removed a long time agoIan Lance Taylor1996-09-022-32/+0
* * v850-dis.c (disassemble): Handle insertion of ',', '[' andJeff Law1996-08-312-80/+89
* * v850-dis.c (print_insn_v850): Properly handle disassemblingJeff Law1996-08-312-2/+21
* * v850-dis.c (v850_cc_names): Fix stupid thinkos.Jeff Law1996-08-312-2/+3
* * v850-dis.c (v850_reg_names): Define.Jeff Law1996-08-313-3/+62
* * v850-dis.c: New file. Skeleton for disassembler support.Jeff Law1996-08-311-0/+78
* * v850-dis.c: New file. Skeleton for disassembler support.Jeff Law1996-08-312-2/+9
* * v850-opc.c (insert_d8_7, extract_d8_7): New functions.Jeff Law1996-08-312-19/+90
* * v850-opc.c (insert_d16_15, extract_d16_15): New functions.Jeff Law1996-08-312-11/+52
* * v850-opc.c (insert_d9, insert_d22): Slightly improve errorJeff Law1996-08-312-1/+10
* * v850-opc.c: Add notes about needing special insert/extractJeff Law1996-08-312-0/+9
* * v850-opc.c (insert_d22, extract_d22): New functions.Jeff Law1996-08-312-2/+33
* * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flagJ.T. Conklin1996-08-312-2/+7
* * v850-opc.c (v850_operands): Define SR2 operand.Jeff Law1996-08-302-1/+9
* * v850-opc.c (v850_opcodes): Fix opcode specs forJeff Law1996-08-292-5/+10
* * v850-opc.c (v850_opcodes): Add null opcode to mark theJeff Law1996-08-282-5/+31
* Remove v850-opc.c from things-to-keepJ.T. Conklin1996-08-261-1/+0
* * v850-opc.c (v850_operands): Define EP operand.Jeff Law1996-08-232-5/+12
* * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"Jeff Law1996-08-232-7/+7
* * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]Jeff Law1996-08-232-9/+12
* * v850-opc.c (v850_operands): "not" is a two byte insn.Jeff Law1996-08-232-1/+3
* * v850-opc.c (v850_opcodes): Correct bit pattern for setf.Jeff Law1996-08-232-1/+3
* * v850-opc.c (v850_operands): D16 inserts at offset 16!Jeff Law1996-08-232-1/+3
* * v850-opc.c (two): Get order of words correct.Jeff Law1996-08-232-1/+3
* * v850-opc.c (v850_operands): I16 inserts at offset 16!Jeff Law1996-08-232-1/+3
* * v850-opc.c (v850_operands): Add "SR1" and "SR2" for systemJeff Law1996-08-232-2/+12
* * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. FixJeff Law1996-08-232-2/+3
* * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode.Jeff Law1996-08-232-1/+3
* * v850-opc.c (v850_opcodes): Add initializer for size fieldJeff Law1996-08-232-84/+87
* * v850-opc.c (v850_operands): D6 -> DS7. References changed.Jeff Law1996-08-232-15/+29
* * v850-opc.c (v850_operansd): 3-bit immediate for bit insnsJeff Law1996-08-232-1/+4
* Add V850_OPERAND_SIGNED flag as appropriate, create new unsigned IMM5 operandJ.T. Conklin1996-08-231-8/+11
* * v850-opc.c (v850_opcodes): Correct short store half (sst.h) andJeff Law1996-08-232-1/+6
* start writing functions for extracting and inserting unusual operandsJ.T. Conklin1996-08-231-6/+37
* * v850-opc.c (v850_operands): Added insert and extract fields,J.T. Conklin1996-08-232-15/+22
* * v850-opc.c (v850_opcodes): Enable "trap".Jeff Law1996-08-222-2/+2
* * v850-opc.c (v850_opcodes): Fix order of displacementJeff Law1996-08-222-4/+9
* minimal setf supportJ.T. Conklin1996-08-221-1/+3
* Stub in load and store insns. Fix order of jarl operandsJ.T. Conklin1996-08-221-5/+19
* Arggh. B3. shift counts are from the start of each half-word apparently.Jeff Law1996-08-221-1/+1
* Fix thinko in B3.Jeff Law1996-08-221-1/+1
* * v850-opc.c (v850_operands): Add "B3" support.Jeff Law1996-08-222-8/+14
* * v850-ope.c ("jmp"): R1 is only operand.Jeff Law1996-08-222-1/+3
* * v850-opc.c: Close unterminated comment.Jeff Law1996-08-222-1/+5
* * v850-opc.c: Add flags field to struct v850_operands, add moveJ.T. Conklin1996-08-222-22/+35
* * Makefile.in (ALL_MACHINES): Add v850-opc.o.J.T. Conklin1996-08-203-0/+239
* * sparc-dis.c (print_insn_sparc): Handle little endian sparcs.David Edelsohn1996-08-191-0/+12
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