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ppe42-binutils
binutils-2_24-ppe42
GNU Binutils for the PPE42
Raptor Computing Systems
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opcodes
/
i386-dis.c
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Author
Age
Files
Lines
*
Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn
H.J. Lu
2013-10-12
1
-2
/
+2
*
opcodes/
Roland McGrath
2013-10-11
1
-20
/
+28
*
Remove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3F
H.J. Lu
2013-08-19
1
-2
/
+0
*
Add Intel AVX-512 support
H.J. Lu
2013-07-26
1
-31
/
+1306
*
Support Intel SHA
H.J. Lu
2013-07-25
1
-7
/
+49
*
Support Intel MPX
H.J. Lu
2013-07-24
1
-47
/
+126
*
Properly check address mode for SIB
H.J. Lu
2013-03-27
1
-4
/
+4
*
Implement Intel SMAP instructions
H.J. Lu
2013-02-19
1
-0
/
+2
*
gas/testsuite/
Roland McGrath
2012-10-24
1
-58
/
+61
*
gas/testsuite/
Roland McGrath
2012-08-07
1
-0
/
+30
*
gas/testsuite/
Roland McGrath
2012-08-06
1
-6
/
+12
*
gas/testsuite/
Roland McGrath
2012-08-06
1
-30
/
+34
*
Use vex_len_table in xop_table
H.J. Lu
2012-07-19
1
-8
/
+56
*
Implement RDRSEED, ADX and PRFCHW instructions
H.J. Lu
2012-07-16
1
-1
/
+11
*
Implement Intel Transactional Synchronization Extensions
H.J. Lu
2012-02-08
1
-60
/
+175
*
Add vmfunc
H.J. Lu
2012-01-13
1
-0
/
+3
*
PR binutils/13348
Nick Clifton
2011-10-26
1
-1
/
+1
*
opcodes/
Quentin Neill
2011-08-02
1
-1
/
+1
*
Check R_X86_64_32 overflow and allow R_X86_64_64 for x32.
H.J. Lu
2011-08-01
1
-33
/
+11
*
Add initial Intel K1OM support.
H.J. Lu
2011-07-22
1
-3
/
+8
*
Update rorxS.
H.J. Lu
2011-07-01
1
-1
/
+1
*
Fix rorx in BMI2.
H.J. Lu
2011-06-30
1
-1
/
+1
*
Re-indent prefix_table.
H.J. Lu
2011-06-21
1
-2
/
+2
*
Support AVX Programming Reference (June, 2011).
H.J. Lu
2011-06-10
1
-960
/
+840
*
2011-02-09 Michael Snyder <msnyder@vmware.com>
Michael Snyder
2011-02-09
1
-5
/
+5
*
Properly sign-extend byte.
H.J. Lu
2011-01-18
1
-3
/
+28
*
Add support for TBM instructions.
Quentin Neill
2011-01-17
1
-5
/
+28
*
Implement BMI instructions.
H.J. Lu
2011-01-05
1
-4
/
+80
*
Add VexGdq.
H.J. Lu
2011-01-04
1
-2
/
+8
*
Add x86-64 ILP32 support.
H.J. Lu
2010-12-31
1
-0
/
+5
*
Remove duplicated RMAL.
H.J. Lu
2010-10-02
1
-1
/
+0
*
Fix "pushw imm16" for x86-64 disassembler.
H.J. Lu
2010-08-31
1
-38
/
+30
*
Replace Eb with Mb on prefetch and prefetchw.
H.J. Lu
2010-08-17
1
-2
/
+2
*
Add ud1 to x86.
H.J. Lu
2010-08-06
1
-2
/
+2
*
Add 0F to VEX opcode enums.
H.J. Lu
2010-07-28
1
-2259
/
+2259
*
Replace rdrnd with rdrand.
H.J. Lu
2010-07-05
1
-1
/
+1
*
Support AVX Programming Reference (June, 2010)
H.J. Lu
2010-07-01
1
-3
/
+52
*
Add SIB.
H.J. Lu
2010-05-26
1
-4
/
+28
*
Remove extra breack.
H.J. Lu
2010-04-16
1
-1
/
+0
*
Return bad_opcode on unknown bits in opcode.
H.J. Lu
2010-04-16
1
-5
/
+17
*
bfd/ChangeLog
Nick Clifton
2010-04-09
1
-8
/
+0
*
2010-03-22 Sebastian Pop <sebastian.pop@amd.com>
Sebastian Pop
2010-03-23
1
-18
/
+4
*
Update copyright.
H.J. Lu
2010-02-11
1
-1
/
+1
*
2010-02-10 Quentin Neill <quentin.neill@amd.com>
Sebastian Pop
2010-02-11
1
-2
/
+73
*
Allow VL=1 on scalar FMA instructions.
H.J. Lu
2010-01-28
1
-13
/
+18
*
Allow VL=1 on AVX scalar instructions.
H.J. Lu
2010-01-27
1
-44
/
+125
*
Remove trailing { Bad_Opcode }.
H.J. Lu
2010-01-24
1
-1
/
+0
*
Remove trailing { Bad_Opcode } in vex_len_table.
H.J. Lu
2010-01-24
1
-1
/
+0
*
Remove trailing { Bad_Opcode }.
H.J. Lu
2010-01-24
1
-1
/
+0
*
Remove trailing "(bad)" entries and replace { "(bad)", { XX } }
H.J. Lu
2010-01-24
1
-3561
/
+2647
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