diff options
Diffstat (limited to 'sim/sh/gencode.c')
| -rw-r--r-- | sim/sh/gencode.c | 37 |
1 files changed, 18 insertions, 19 deletions
diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c index 52e611f369..9ea898f702 100644 --- a/sim/sh/gencode.c +++ b/sim/sh/gencode.c @@ -4,7 +4,7 @@ Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com - This file is part of SH sim + This file is part of SH sim. THIS SOFTWARE IS NOT COPYRIGHTED @@ -20,7 +20,7 @@ */ /* This program generates the opcode table for the assembler and - the simulator code + the simulator code. -t prints a pretty table for the assembler manual -s generates the simulator code jump table @@ -287,7 +287,7 @@ op tab[] = /* sh2e */ { "", "", "fdiv <FREG_M>,<FREG_N>", "1111nnnnmmmm0011", "FP_OP (n, /, m);", - "/* FIXME: check for DP and (n & 1) == 0? */", + "/* FIXME: check for DP and (n & 1) == 0? */", }, /* sh4 */ @@ -309,13 +309,13 @@ op tab[] = /* sh2e */ { "", "", "fldi0 <FREG_N>", "1111nnnn10001101", "SET_FR (n, (float) 0.0);", - "/* FIXME: check for DP and (n & 1) == 0? */", + "/* FIXME: check for DP and (n & 1) == 0? */", }, /* sh2e */ { "", "", "fldi1 <FREG_N>", "1111nnnn10011101", "SET_FR (n, (float) 1.0);", - "/* FIXME: check for DP and (n & 1) == 0? */", + "/* FIXME: check for DP and (n & 1) == 0? */", }, /* sh2e */ @@ -443,7 +443,8 @@ op tab[] = "}", }, - /* sh4: See fmov instructions above for move to/from extended fp registers */ + /* sh4: + See fmov instructions above for move to/from extended fp registers. */ /* sh2e */ { "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010", @@ -662,11 +663,11 @@ op tab[] = }, { "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111", - "macl (&R0,memory,n,m);", + "macl (&R0, memory, n, m);", }, { "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111", - "macw (&R0,memory,n,m,endianw);", + "macw (&R0, memory, n, m, endianw);", }, { "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....", @@ -1192,7 +1193,7 @@ op tab[] = { "0", "", "trapa #<imm>", "11000011i8*1....", "long imm = 0xff & i;", "if (i < 20 || i == 33 || i == 34 || i == 0xc3)", - " nip += trap (i, R, PC, memory, maskl, maskw,endianw);", + " nip += trap (i, R, PC, memory, maskl, maskw, endianw);", #if 0 "else {", /* SH-[12] */ @@ -1242,10 +1243,10 @@ op tab[] = #if 0 { "divs.l <REG_M>,<REG_N>", "0100nnnnmmmm1110", - "divl (0,R[n],R[m]);", + "divl (0, R[n], R[m]);", }, { "divu.l <REG_M>,<REG_N>", "0100nnnnmmmm1101", - "divl (0,R[n],R[m]);", + "divl (0, R[n], R[m]);", }, #endif @@ -2262,8 +2263,6 @@ gengastab () { printf ("%s %-30s\n", p->code, p->name); } - - } static unsigned char table[1 << 16]; @@ -2395,7 +2394,7 @@ expand_opcode (val, i, s) } /* Print the jump table used to index an opcode into a switch - statement entry. */ + statement entry. */ static void dumptable (name, size, start) @@ -2643,7 +2642,7 @@ gensim_caselist (p) printf (" TL (n);\n"); { - /* Do the refs */ + /* Do the refs. */ char *r; for (r = p->refs; *r; r++) { @@ -2666,7 +2665,7 @@ gensim_caselist (p) printf (" }\n"); { - /* Do the defs */ + /* Do the defs. */ char *r; for (r = p->defs; *r; r++) { @@ -2975,12 +2974,12 @@ main (ac, av) int ac; char **av; { - /* verify the table before anything else */ + /* Verify the table before anything else. */ { op *p; for (p = tab; p->name; p++) { - /* check that the code field contains 16 bits */ + /* Check that the code field contains 16 bits. */ if (strlen (p->code) != 16) { fprintf (stderr, "Code `%s' length wrong (%d) for `%s'\n", @@ -2990,7 +2989,7 @@ main (ac, av) } } - /* now generate the requested data */ + /* Now generate the requested data. */ if (ac > 1) { if (strcmp (av[1], "-t") == 0) |
