diff options
Diffstat (limited to 'ld/testsuite/ld-powerpc')
28 files changed, 731 insertions, 2 deletions
diff --git a/ld/testsuite/ld-powerpc/apuinfo.rd b/ld/testsuite/ld-powerpc/apuinfo.rd index 7a27bc0117..7a09d2f3c9 100644 --- a/ld/testsuite/ld-powerpc/apuinfo.rd +++ b/ld/testsuite/ld-powerpc/apuinfo.rd @@ -6,6 +6,7 @@ #target: powerpc-eabi* Hex dump of section '.PPC.EMB.apuinfo': - 0x00000000 00000008 0000001c 00000002 41505569 ............APUi + 0x00000000 00000008 00000020 00000002 41505569 ....... ....APUi 0x00000010 6e666f00 00420001 00430001 00410001 nfo..B...C...A.. - 0x00000020 01020001 01010001 00400001 01000001 .........@...... + 0x00000020 01020001 01010001 00400001 01040001 .........@...... + 0x00000030 01000001 ....$ diff --git a/ld/testsuite/ld-powerpc/powerpc.exp b/ld/testsuite/ld-powerpc/powerpc.exp index 566272d6ee..8b7e7fd0a1 100644 --- a/ld/testsuite/ld-powerpc/powerpc.exp +++ b/ld/testsuite/ld-powerpc/powerpc.exp @@ -215,6 +215,33 @@ set ppc64elftests { {{objdump -s tocopt5.d}} "tocopt5"} } +set ppceabitests { + {"VLE multiple segments 1" "-T vle-multiseg-1.ld" + "-mregnames -mvle" {vle-multiseg.s} + {{readelf "-l" vle-multiseg-1.d}} "vle-multiseg-1"} + {"VLE multiple segments 2" "-T vle-multiseg-2.ld" + "-mregnames -mvle" {vle-multiseg.s} + {{readelf "-l" vle-multiseg-2.d}} "vle-multiseg-2"} + {"VLE multiple segments 3" "-T vle-multiseg-3.ld" + "-mregnames -mvle" {vle-multiseg.s} + {{readelf "-l" vle-multiseg-3.d}} "vle-multiseg-3"} + {"VLE multiple segments 4" "-T vle-multiseg-4.ld" + "-mregnames -mvle" {vle-multiseg.s} + {{readelf "-l" vle-multiseg-4.d}} "vle-multiseg-4"} + {"VLE multiple segments 5" "-T vle-multiseg-5.ld" + "-mregnames -mvle" {vle-multiseg.s} + {{readelf "-l" vle-multiseg-5.d}} "vle-multiseg-5"} + {"VLE relocations 1" "" + "-mvle" {vle-reloc-1.s vle-reloc-def-1.s} + {{objdump "-Mvle -d" vle-reloc-1.d}} "vle-reloc-1"} + {"VLE relocations 2" "" + "-mvle" {vle-reloc-2.s vle-reloc-def-2.s} + {{objdump "-Mvle -d" vle-reloc-2.d}} "vle-reloc-2"} + {"VLE relocations 3" "" + "-mvle" {vle-reloc-3.s vle-reloc-def-3.s} + {{objdump "-Mvle -d" vle-reloc-3.d}} "vle-reloc-3"} +} + run_ld_link_tests $ppcelftests @@ -223,6 +250,10 @@ if [ supports_ppc64 ] then { run_dump_test "relbrlt" } +if { [istarget "powerpc*-eabi*"] } { + run_ld_link_tests $ppceabitests +} + run_dump_test "plt1" run_dump_test "attr-gnu-4-00" @@ -251,3 +282,5 @@ run_dump_test "attr-gnu-8-31" run_dump_test "attr-gnu-12-11" run_dump_test "attr-gnu-12-21" + +run_dump_test "vle-multiseg-6" diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-1.d b/ld/testsuite/ld-powerpc/vle-multiseg-1.d new file mode 100644 index 0000000000..d9554a11b2 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-1.d @@ -0,0 +1,14 @@ + +Elf file type is EXEC.* +Entry point 0x0 +There are 2 program headers, starting at offset [0-9]+ + +Program Headers: + Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align + LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+ + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + + Section to Segment mapping: + Segment Sections... + 00 .data + 01 .text_vle .text_iv .iv_handlers diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-1.ld b/ld/testsuite/ld-powerpc/vle-multiseg-1.ld new file mode 100644 index 0000000000..f2ff319fda --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-1.ld @@ -0,0 +1,17 @@ +SECTIONS +{ + .data 0x00000400 : + { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) } + .text_vle 0x00001000 : + { + . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) + } + .text_iv . : { . = ALIGN(16); *(.text_iv) } + .iv_handlers 0x0001F000 : { *(.iv_handlers) } +} diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-2.d b/ld/testsuite/ld-powerpc/vle-multiseg-2.d new file mode 100644 index 0000000000..9d83bb50fa --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-2.d @@ -0,0 +1,16 @@ + +Elf file type is EXEC.* +Entry point 0x0 +There are 3 program headers, starting at offset [0-9]+ + +Program Headers: + Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+ + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + + Section to Segment mapping: + Segment Sections... + 00 .text_vle + 01 .data + 02 .text_iv .iv_handlers diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-2.ld b/ld/testsuite/ld-powerpc/vle-multiseg-2.ld new file mode 100644 index 0000000000..2320b61c2a --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-2.ld @@ -0,0 +1,17 @@ +SECTIONS +{ + .text_vle 0x00001000 : + { + . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) + } + .data 0x00001400 : + { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) } + .text_iv . : { . = ALIGN(16); *(.text_iv) } + .iv_handlers 0x0001F000 : { *(.iv_handlers) } +} diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-3.d b/ld/testsuite/ld-powerpc/vle-multiseg-3.d new file mode 100644 index 0000000000..957b990dee --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-3.d @@ -0,0 +1,16 @@ + +Elf file type is EXEC.* +Entry point 0x0 +There are 3 program headers, starting at offset [0-9]+ + +Program Headers: + Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+ + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + + Section to Segment mapping: + Segment Sections... + 00 .text_vle .text_iv + 01 .data + 02 .iv_handlers diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-3.ld b/ld/testsuite/ld-powerpc/vle-multiseg-3.ld new file mode 100644 index 0000000000..0ed2f44c54 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-3.ld @@ -0,0 +1,17 @@ +SECTIONS +{ + .text_vle 0x00001000 : + { + . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) + } + .text_iv . : { . = ALIGN(16); *(.text_iv) } + .data 0x00001400 : + { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) } + .iv_handlers 0x0001F000 : { *(.iv_handlers) } +} diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-4.d b/ld/testsuite/ld-powerpc/vle-multiseg-4.d new file mode 100644 index 0000000000..9edbe06575 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-4.d @@ -0,0 +1,14 @@ + +Elf file type is EXEC.* +Entry point 0x0 +There are 2 program headers, starting at offset [0-9]+ + +Program Headers: + Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+ + + Section to Segment mapping: + Segment Sections... + 00 .text_vle .text_iv .iv_handlers + 01 .data diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-4.ld b/ld/testsuite/ld-powerpc/vle-multiseg-4.ld new file mode 100644 index 0000000000..503fe06eaf --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-4.ld @@ -0,0 +1,17 @@ +SECTIONS +{ + .text_vle 0x00001000 : + { + . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) + } + .text_iv . : { . = ALIGN(16); *(.text_iv) } + .iv_handlers 0x0001F000 : { *(.iv_handlers) } + .data 0x00020400 : + { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) } +} diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-5.d b/ld/testsuite/ld-powerpc/vle-multiseg-5.d new file mode 100644 index 0000000000..957b990dee --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-5.d @@ -0,0 +1,16 @@ + +Elf file type is EXEC.* +Entry point 0x0 +There are 3 program headers, starting at offset [0-9]+ + +Program Headers: + Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+ + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + + Section to Segment mapping: + Segment Sections... + 00 .text_vle .text_iv + 01 .data + 02 .iv_handlers diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-5.ld b/ld/testsuite/ld-powerpc/vle-multiseg-5.ld new file mode 100644 index 0000000000..4000021748 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-5.ld @@ -0,0 +1,44 @@ + +MEMORY +{ + code_rom (rxw) : org = 0x00001000, len = 0x1EF000 + irpt_rom (rx) : org = 0x001F0000, len = 0x2000 + int__ram (rxw) : org = 0x40000000, len = 256K +} + +REGION_ALIAS("INTR", irpt_rom) +REGION_ALIAS("CODE", code_rom) +REGION_ALIAS("RODATA", code_rom) +REGION_ALIAS("RAM", int__ram) + +SECTIONS +{ + .iv_handlers : + { + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.iv_handlers) + } > INTR + + .text_vle : + { + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) + } > CODE + + .rodata : + { + *(.rodata) + } > RODATA + + .data : + { + *(.data) + *(.data.*) + *(.ctors) + *(.dtors) + } > RAM AT>RODATA + +} diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-6.d b/ld/testsuite/ld-powerpc/vle-multiseg-6.d new file mode 100644 index 0000000000..5c3c21040a --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-6.d @@ -0,0 +1,25 @@ +#source: vle-multiseg-6a.s -mregnames -mvle +#source: vle-multiseg-6b.s +#source: vle-multiseg-6c.s +#source: vle-multiseg-6d.s -mregnames -mvle +#ld: -T vle-multiseg-6.ld +#target: powerpc-*-* +#readelf: -l + +Elf file type is EXEC.* +Entry point 0x[0-9a-f]+ +There are 4 program headers, starting at offset [0-9]+ + +Program Headers: + Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align + LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+ + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+ + + Section to Segment mapping: + Segment Sections... + 00 .data + 01 .text_vle + 02 .text_iv + 03 .text diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-6.ld b/ld/testsuite/ld-powerpc/vle-multiseg-6.ld new file mode 100644 index 0000000000..c8d88dd831 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-6.ld @@ -0,0 +1,37 @@ +MEMORY +{ + vle_seg1 (rxw): org = 0x00000000, len = 0x10000 + vle_seg2 (rxw): org = 0x00100000, len = 0x10000 + nonvle_seg (rxw): org = 0x001F0000, len = 0x20000 +} +SECTIONS +{ + .data 0x00000100 : + { + *(.data) + *(.ctors) + *(.dtors) + *(.eh_frame) + *(.jcr) + } + .text_vle 0x00001000 : + { + . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text*) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init*) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini*) + } > vle_seg1 + + .text_iv 0x100000 : + { + . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_iv) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.iv_handlers) + } >vle_seg2 + + .text 0x101000 : + { + . = ALIGN(16); + INPUT_SECTION_FLAGS (!SHF_PPC_VLE) *(.text*) + } +} diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-6a.s b/ld/testsuite/ld-powerpc/vle-multiseg-6a.s new file mode 100644 index 0000000000..a50afae569 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-6a.s @@ -0,0 +1,47 @@ + .text + + e_stw r12, 0x4C(r1) + e_stw r11, 0x48(r1) + e_stw r10, 0x44(r1) + e_stw r9, 0x40(r1) + e_stw r8, 0x3C(r1) + e_stw r7, 0x38(r1) + e_stw r6, 0x34(r1) + e_stw r5, 0x30(r1) + e_stw r4, 0x2c(r1) + + .globl IV_table + .section ".iv_handlers", "ax" +IV_table: + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 +dummy: + se_nop + e_b dummy + + .section ".text_iv", "ax" + e_lis r3, IV_table@h + mtivpr r3 + e_li r3, IV_table@l+0x00 + mtivor0 r3 + e_li r3, IV_table@l+0x10 + mtivor1 r3 + e_li r3, IV_table@l+0x20 + mtivor2 r3 + + .data + .long 0xdeadbeef diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-6b.s b/ld/testsuite/ld-powerpc/vle-multiseg-6b.s new file mode 100644 index 0000000000..10fcf20cbf --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-6b.s @@ -0,0 +1,6 @@ + .text + + and. 3,4,5 + and 3,4,5 + andc 13,14,15 + andc. 16,17,18 diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-6c.s b/ld/testsuite/ld-powerpc/vle-multiseg-6c.s new file mode 100644 index 0000000000..10fcf20cbf --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-6c.s @@ -0,0 +1,6 @@ + .text + + and. 3,4,5 + and 3,4,5 + andc 13,14,15 + andc. 16,17,18 diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-6d.s b/ld/testsuite/ld-powerpc/vle-multiseg-6d.s new file mode 100644 index 0000000000..a8c6fcc883 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-6d.s @@ -0,0 +1,9 @@ + .section ".text_iv", "ax" + e_lis r3, IV_table@h + mtivpr r3 + e_li r3, IV_table@l+0x00 + mtivor0 r3 + e_li r3, IV_table@l+0x10 + mtivor1 r3 + e_li r3, IV_table@l+0x20 + mtivor2 r3 diff --git a/ld/testsuite/ld-powerpc/vle-multiseg.s b/ld/testsuite/ld-powerpc/vle-multiseg.s new file mode 100644 index 0000000000..b0c08862a5 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg.s @@ -0,0 +1,50 @@ +# Make up several VLE text sections which the linker script will put into +# separate output sections. We will then check for separate load segments. +# .include "mpc5500_usrdefs.inc" +# .section ".text_vle" + + e_stw r12, 0x4C(r1) + e_stw r11, 0x48(r1) + e_stw r10, 0x44(r1) + e_stw r9, 0x40(r1) + e_stw r8, 0x3C(r1) + e_stw r7, 0x38(r1) + e_stw r6, 0x34(r1) + e_stw r5, 0x30(r1) + e_stw r4, 0x2c(r1) + + .globl IV_table + .section ".iv_handlers", "ax" +IV_table: + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 + e_b dummy + .align 4 +dummy: + se_nop + e_b dummy + + .section ".text_iv", "ax" + e_lis r3, IV_table@h + mtivpr r3 + e_li r3, IV_table@l+0x00 + mtivor0 r3 + e_li r3, IV_table@l+0x10 + mtivor1 r3 + e_li r3, IV_table@l+0x20 + mtivor2 r3 + + .data + .long 0xdeadbeef diff --git a/ld/testsuite/ld-powerpc/vle-reloc-1.d b/ld/testsuite/ld-powerpc/vle-reloc-1.d new file mode 100644 index 0000000000..0f5927164a --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-1.d @@ -0,0 +1,29 @@ +.*: file format .* + + +Disassembly of section .text: + +01800054 <sub1>: + 1800054: 00 04 se_blr + +01800056 <sub2>: + 1800056: 00 04 se_blr + +01800058 <vle_reloc>: + 1800058: e8 fe se_b 1800054 <sub1> + 180005a: e9 fd se_bl 1800054 <sub1> + 180005c: e1 fd se_ble 1800056 <sub2> + 180005e: e6 fc se_beq 1800056 <sub2> + 1800060: 78 00 00 10 e_b 1800070 <sub3> + 1800064: 78 00 00 0f e_bl 1800072 <sub4> + 1800068: 7a 05 00 0c e_ble cr1,1800074 <sub5> + 180006c: 7a 1a 00 09 e_beql cr2,1800074 <sub5> + +01800070 <sub3>: + 1800070: 00 04 se_blr + +01800072 <sub4>: + 1800072: 00 04 se_blr + +01800074 <sub5>: + 1800074: 00 04 se_blr diff --git a/ld/testsuite/ld-powerpc/vle-reloc-1.s b/ld/testsuite/ld-powerpc/vle-reloc-1.s new file mode 100644 index 0000000000..e56a22ba64 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-1.s @@ -0,0 +1,18 @@ + .section .text +sub1: + se_blr + +sub2: + se_blr + + .section .text +vle_reloc: + se_b sub1 + se_bl sub1 + se_bc 0,1,sub2 + se_bc 1,2,sub2 + + e_b sub3 + e_bl sub4 + e_bc 0,5,sub5 + e_bcl 1,10,sub5 diff --git a/ld/testsuite/ld-powerpc/vle-reloc-2.d b/ld/testsuite/ld-powerpc/vle-reloc-2.d new file mode 100644 index 0000000000..1e1c9d489c --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-2.d @@ -0,0 +1,87 @@ +.*: file format .* + +Disassembly of section .text: + +01800094 <sub1>: + 1800094: 00 04 se_blr +01800096 <sub2>: + 1800096: 00 04 se_blr +01800098 <vle_reloc_2>: + 1800098: 70 20 c1 c2 e_or2i r1,450 + 180009c: 70 40 c1 81 e_or2i r2,385 + 18000a0: 70 60 c1 81 e_or2i r3,385 + 18000a4: 70 80 c1 ce e_or2i r4,462 + 18000a8: 70 a0 c1 80 e_or2i r5,384 + 18000ac: 70 40 c1 81 e_or2i r2,385 + 18000b0: 70 20 c9 c2 e_and2i. r1,450 + 18000b4: 70 40 c9 81 e_and2i. r2,385 + 18000b8: 70 60 c9 81 e_and2i. r3,385 + 18000bc: 70 80 c9 ce e_and2i. r4,462 + 18000c0: 70 a0 c9 80 e_and2i. r5,384 + 18000c4: 70 40 c9 81 e_and2i. r2,385 + 18000c8: 70 20 d1 c2 e_or2is r1,450 + 18000cc: 70 40 d1 81 e_or2is r2,385 + 18000d0: 70 60 d1 81 e_or2is r3,385 + 18000d4: 70 80 d1 ce e_or2is r4,462 + 18000d8: 70 a0 d1 80 e_or2is r5,384 + 18000dc: 70 40 d1 81 e_or2is r2,385 + 18000e0: 70 20 e1 c2 e_lis r1,450 + 18000e4: 70 40 e1 81 e_lis r2,385 + 18000e8: 70 60 e1 81 e_lis r3,385 + 18000ec: 70 80 e1 ce e_lis r4,462 + 18000f0: 70 a0 e1 80 e_lis r5,384 + 18000f4: 70 40 e1 81 e_lis r2,385 + 18000f8: 70 20 e9 c2 e_and2is. r1,450 + 18000fc: 70 40 e9 81 e_and2is. r2,385 + 1800100: 70 60 e9 81 e_and2is. r3,385 + 1800104: 70 80 e9 ce e_and2is. r4,462 + 1800108: 70 a0 e9 80 e_and2is. r5,384 + 180010c: 70 40 e9 81 e_and2is. r2,385 + 1800110: 70 01 99 c2 e_cmp16i r1,450 + 1800114: 70 02 99 81 e_cmp16i r2,385 + 1800118: 70 03 99 81 e_cmp16i r3,385 + 180011c: 70 04 99 ce e_cmp16i r4,462 + 1800120: 70 05 99 80 e_cmp16i r5,384 + 1800124: 70 02 99 81 e_cmp16i r2,385 + 1800128: 70 01 a9 c2 e_cmpl16i r1,450 + 180012c: 70 02 a9 81 e_cmpl16i r2,385 + 1800130: 70 03 a9 81 e_cmpl16i r3,385 + 1800134: 70 04 a9 ce e_cmpl16i r4,462 + 1800138: 70 05 a9 80 e_cmpl16i r5,384 + 180013c: 70 02 a9 81 e_cmpl16i r2,385 + 1800140: 70 01 b1 c2 e_cmph16i r1,450 + 1800144: 70 02 b1 81 e_cmph16i r2,385 + 1800148: 70 03 b1 81 e_cmph16i r3,385 + 180014c: 70 04 b1 ce e_cmph16i r4,462 + 1800150: 70 05 b1 80 e_cmph16i r5,384 + 1800154: 70 02 b1 81 e_cmph16i r2,385 + 1800158: 70 01 b9 c2 e_cmphl16i r1,450 + 180015c: 70 02 b9 81 e_cmphl16i r2,385 + 1800160: 70 03 b9 81 e_cmphl16i r3,385 + 1800164: 70 04 b9 ce e_cmphl16i r4,462 + 1800168: 70 05 b9 80 e_cmphl16i r5,384 + 180016c: 70 02 b9 81 e_cmphl16i r2,385 + 1800170: 70 01 89 c2 e_add2i. r1,450 + 1800174: 70 02 89 81 e_add2i. r2,385 + 1800178: 70 03 89 81 e_add2i. r3,385 + 180017c: 70 04 89 ce e_add2i. r4,462 + 1800180: 70 05 89 80 e_add2i. r5,384 + 1800184: 70 02 89 81 e_add2i. r2,385 + 1800188: 70 01 91 c2 e_add2is r1,450 + 180018c: 70 02 91 81 e_add2is r2,385 + 1800190: 70 03 91 81 e_add2is r3,385 + 1800194: 70 04 91 ce e_add2is r4,462 + 1800198: 70 05 91 80 e_add2is r5,384 + 180019c: 70 02 91 81 e_add2is r2,385 + 18001a0: 70 01 a1 c2 e_mull2i r1,450 + 18001a4: 70 02 a1 81 e_mull2i r2,385 + 18001a8: 70 03 a1 81 e_mull2i r3,385 + 18001ac: 70 04 a1 ce e_mull2i r4,462 + 18001b0: 70 05 a1 80 e_mull2i r5,384 + 18001b4: 70 02 a1 81 e_mull2i r2,385 +018001b8 <sub3>: + 18001b8: 00 04 se_blr +018001ba <sub4>: + 18001ba: 00 04 se_blr +018001bc <sub5>: + 18001bc: 00 04 se_blr diff --git a/ld/testsuite/ld-powerpc/vle-reloc-2.s b/ld/testsuite/ld-powerpc/vle-reloc-2.s new file mode 100644 index 0000000000..34cc32d7e8 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-2.s @@ -0,0 +1,92 @@ + .section .text +sub1: + se_blr + +sub2: + se_blr + + .section .text +vle_reloc_2: + e_or2i 1, low@l + e_or2i 2, high@h + e_or2i 3, high_adjust@ha + e_or2i 4, low_sdarel@sdarel@l + e_or2i 5, high_sdarel@sdarel@h + e_or2i 2, high_adjust_sdarel@sdarel@ha + + e_and2i. 1, low@l + e_and2i. 2, high@h + e_and2i. 3, high_adjust@ha + e_and2i. 4, low_sdarel@sdarel@l + e_and2i. 5, high_sdarel@sdarel@h + e_and2i. 2, high_adjust_sdarel@sdarel@ha + + e_or2is 1, low@l + e_or2is 2, high@h + e_or2is 3, high_adjust@ha + e_or2is 4, low_sdarel@sdarel@l + e_or2is 5, high_sdarel@sdarel@h + e_or2is 2, high_adjust_sdarel@sdarel@ha + + e_lis 1, low@l + e_lis 2, high@h + e_lis 3, high_adjust@ha + e_lis 4, low_sdarel@sdarel@l + e_lis 5, high_sdarel@sdarel@h + e_lis 2, high_adjust_sdarel@sdarel@ha + + e_and2is. 1, low@l + e_and2is. 2, high@h + e_and2is. 3, high_adjust@ha + e_and2is. 4, low_sdarel@sdarel@l + e_and2is. 5, high_sdarel@sdarel@h + e_and2is. 2, high_adjust_sdarel@sdarel@ha + + e_cmp16i 1, low@l + e_cmp16i 2, high@h + e_cmp16i 3, high_adjust@ha + e_cmp16i 4, low_sdarel@sdarel@l + e_cmp16i 5, high_sdarel@sdarel@h + e_cmp16i 2, high_adjust_sdarel@sdarel@ha + + e_cmpl16i 1, low@l + e_cmpl16i 2, high@h + e_cmpl16i 3, high_adjust@ha + e_cmpl16i 4, low_sdarel@sdarel@l + e_cmpl16i 5, high_sdarel@sdarel@h + e_cmpl16i 2, high_adjust_sdarel@sdarel@ha + + e_cmph16i 1, low@l + e_cmph16i 2, high@h + e_cmph16i 3, high_adjust@ha + e_cmph16i 4, low_sdarel@sdarel@l + e_cmph16i 5, high_sdarel@sdarel@h + e_cmph16i 2, high_adjust_sdarel@sdarel@ha + + e_cmphl16i 1, low@l + e_cmphl16i 2, high@h + e_cmphl16i 3, high_adjust@ha + e_cmphl16i 4, low_sdarel@sdarel@l + e_cmphl16i 5, high_sdarel@sdarel@h + e_cmphl16i 2, high_adjust_sdarel@sdarel@ha + + e_add2i. 1, low@l + e_add2i. 2, high@h + e_add2i. 3, high_adjust@ha + e_add2i. 4, low_sdarel@sdarel@l + e_add2i. 5, high_sdarel@sdarel@h + e_add2i. 2, high_adjust_sdarel@sdarel@ha + + e_add2is 1, low@l + e_add2is 2, high@h + e_add2is 3, high_adjust@ha + e_add2is 4, low_sdarel@sdarel@l + e_add2is 5, high_sdarel@sdarel@h + e_add2is 2, high_adjust_sdarel@sdarel@ha + + e_mull2i 1, low@l + e_mull2i 2, high@h + e_mull2i 3, high_adjust@ha + e_mull2i 4, low_sdarel@sdarel@l + e_mull2i 5, high_sdarel@sdarel@h + e_mull2i 2, high_adjust_sdarel@sdarel@ha diff --git a/ld/testsuite/ld-powerpc/vle-reloc-3.d b/ld/testsuite/ld-powerpc/vle-reloc-3.d new file mode 100644 index 0000000000..e29f4f0786 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-3.d @@ -0,0 +1,8 @@ +.*: file format .* + +Disassembly of section .text: + +01800094 <sda21_test>: + 1800094: 1c ad 80 08 e_add16i r5,r13,-32760 + 1800098: 1c a2 80 04 e_add16i r5,r2,-32764 + 180009c: 70 00 00 ac e_li r0,172 diff --git a/ld/testsuite/ld-powerpc/vle-reloc-3.s b/ld/testsuite/ld-powerpc/vle-reloc-3.s new file mode 100644 index 0000000000..3c7dfae737 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-3.s @@ -0,0 +1,10 @@ + .section .text + .extern exdat1c + .extern exdat2b + .extern exdat1a + .globl sda21_test + +sda21_test: + e_add16i 5, 4, exdat1c@sda21 + e_add16i 5, 4, exdat2b@sda21 + e_add16i 5, 4, exdat0b@sda21 diff --git a/ld/testsuite/ld-powerpc/vle-reloc-def-1.s b/ld/testsuite/ld-powerpc/vle-reloc-def-1.s new file mode 100644 index 0000000000..a879221901 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-def-1.s @@ -0,0 +1,13 @@ + .section .text + .globl sub3 +sub3: + se_blr + + .globl sub4 +sub4: + se_blr + + .globl sub5 +sub5: + se_blr + diff --git a/ld/testsuite/ld-powerpc/vle-reloc-def-2.s b/ld/testsuite/ld-powerpc/vle-reloc-def-2.s new file mode 100644 index 0000000000..363a39fbf6 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-def-2.s @@ -0,0 +1,41 @@ + .section .text + + .globl sub3 +sub3: + se_blr + + .globl sub4 +sub4: + se_blr + + .globl sub5 +sub5: + se_blr + + .section .sdata + .globl low_sdarel +low_sdarel: + .long 2 + + .globl high_adjust_sdarel +high_adjust_sdarel: + .long 0xff + + .section .sdata2 + .globl high_sdarel +high_sdarel: + .long 0xf + + + .data + .globl low +low: + .long 5 + + .globl high +high: + .long 0x10 + + .globl high_adjust +high_adjust: + .long 0xffff diff --git a/ld/testsuite/ld-powerpc/vle-reloc-def-3.s b/ld/testsuite/ld-powerpc/vle-reloc-def-3.s new file mode 100644 index 0000000000..e3b843be08 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-def-3.s @@ -0,0 +1,29 @@ + .section .sdata + .globl exdat1a + .globl exdat1b + .globl exdat1c +exdat1a: .long 6 +exdat1b: .long 7 +exdat1c: .long 8 + + .section .sdata2 + .globl exdat2a + .globl exdat2b + .globl exdat2c +exdat2a: .long 5 +exdat2b: .long 4 +exdat2c: .long 3 + + .section .PPC.EMB.sdata0 + .globl exdat0a + .globl exdat0b + .globl exdat0c +exdat0a: .long 1 +exdat0b: .long 2 +exdat0c: .long 3 + + .section .sbss + .globl exbss1a + .globl exbss1b +exbss1a: .int +exbss1b: .int |
