diff options
| -rw-r--r-- | sim/mips/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/mips/mips3264r2.igen | 11 |
2 files changed, 16 insertions, 0 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 95e23dea9e..4d5bde28da 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,8 @@ +2012-10-04 Chao-ying Fu <fu@mips.com> + Steve Ellcey <sellcey@mips.com> + + * mips/mips3264r2.igen (rdhwr): New. + 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com> * configure.ac: Always link against dv-sockser.o. diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen index c52ec3b2c4..e0b6d5bf64 100644 --- a/sim/mips/mips3264r2.igen +++ b/sim/mips/mips3264r2.igen @@ -241,6 +241,17 @@ } +011111,00000,5.RT,5.RD,00000,111011::32::RDHWR +"rdhwr r<RT>, r<RD>" +*mips32r2: +*mips64r2: +{ + // Return 0 for all hardware registers currently + GPR[RT] = EXTEND32 (0); + TRACE_ALU_RESULT1 (GPR[RT]); +} + + 011111,00000,5.RT,5.RD,00010,100000::32::WSBH "wsbh r<RD>, r<RT>" *mips32r2: |
