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authorJason Molenda <jmolenda@apple.com>1999-11-02 04:44:47 +0000
committerJason Molenda <jmolenda@apple.com>1999-11-02 04:44:47 +0000
commit5c44784c11ecc8febfff615b88496c56c9ad5274 (patch)
tree74f9079f5b0ddae1182abf087af8adc02103e149 /sim
parent9503fd8735ec438fcb2fca34afa276e3e6ca94f5 (diff)
downloadppe42-binutils-5c44784c11ecc8febfff615b88496c56c9ad5274.tar.gz
ppe42-binutils-5c44784c11ecc8febfff615b88496c56c9ad5274.zip
import gdb-1999-11-01 snapshot
Diffstat (limited to 'sim')
-rw-r--r--sim/arm/ChangeLog5
-rw-r--r--sim/arm/thumbemu.c2
-rw-r--r--sim/d10v/ChangeLog5
-rw-r--r--sim/d10v/simops.c4
4 files changed, 14 insertions, 2 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index 44b1523854..eb432557bd 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,8 @@
+1999-10-27 Nick Clifton <nickc@cygnus.com>
+
+ * thumbemu.c (ARMul_ThumbDecode): Accept 0xbebe as a thumb
+ breakpoint.
+
1999-10-08 Ulrich Drepper <drepper@cygnus.com>
* armos.c (SWIopen): Always pass third parameter with 0666 since
diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c
index c610b97c55..9a9fe03120 100644
--- a/sim/arm/thumbemu.c
+++ b/sim/arm/thumbemu.c
@@ -325,6 +325,8 @@ ARMul_ThumbDecode (state,pc,tinstr,ainstr)
: 0xE28DDF00) /* ADD */
| (tinstr & 0x007F); /* off7 */
}
+ else if ((tinstr & 0x0F00) == 0x0e00)
+ * ainstr = 0xEF000000 | SWI_Breakpoint;
else
{
/* Format 14 */
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index 6fa21b1de4..0be82fa979 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,8 @@
+Mon Oct 18 18:03:24 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
+
+ * simops.c (OP_3220): Fix trace output for illegal accumulator
+ message.
+
1999-09-14 Nick Clifton <nickc@cygnus.com>
* simops.c: Disable setting of DM bit in PSW.
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index 9d779438b9..5f19ebd9a1 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -2360,7 +2360,7 @@ OP_3220 ()
trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
- reg = SEXT16( GPR (OP[1]));
+ reg = SEXT16 (GPR (OP[1]));
if (reg >= 17 || reg <= -17)
{
@@ -2373,7 +2373,7 @@ OP_3220 ()
if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: value to shift 0x%x out of range.\n", tmp);
+ (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
State.exception = SIGILL;
return;
}
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