summaryrefslogtreecommitdiffstats
path: root/sim/testsuite
diff options
context:
space:
mode:
authorChris Demetriou <cgd@google.com>2004-04-10 07:11:29 +0000
committerChris Demetriou <cgd@google.com>2004-04-10 07:11:29 +0000
commit5dbb7b5a1d1498adfae0ff7402eccd5c998efeca (patch)
treef1e99970eb1c7c51dacde524be5e76759a0a2478 /sim/testsuite
parent55dc1ac473bb50ec8d11dd76d680459cea10aeb0 (diff)
downloadppe42-binutils-5dbb7b5a1d1498adfae0ff7402eccd5c998efeca.tar.gz
ppe42-binutils-5dbb7b5a1d1498adfae0ff7402eccd5c998efeca.zip
im/mips/ChangeLog ]
2004-04-10 Chris Demetriou <cgd@broadcom.com> * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New. [ sim/testsuite/sim/mips/ChangeLog ] 2004-04-10 Chris Demetriou <cgd@broadcom.com> * fpu64-ps-sb1.s: New file. * basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s if appropriate.
Diffstat (limited to 'sim/testsuite')
-rw-r--r--sim/testsuite/sim/mips/ChangeLog6
-rw-r--r--sim/testsuite/sim/mips/basic.exp6
-rw-r--r--sim/testsuite/sim/mips/fpu64-ps-sb1.s72
3 files changed, 83 insertions, 1 deletions
diff --git a/sim/testsuite/sim/mips/ChangeLog b/sim/testsuite/sim/mips/ChangeLog
index 3bec86b573..4712274c2b 100644
--- a/sim/testsuite/sim/mips/ChangeLog
+++ b/sim/testsuite/sim/mips/ChangeLog
@@ -1,5 +1,11 @@
2004-04-10 Chris Demetriou <cgd@broadcom.com>
+ * fpu64-ps-sb1.s: New file.
+ * basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s
+ if appropriate.
+
+2004-04-10 Chris Demetriou <cgd@broadcom.com>
+
* fpu64-ps.s: New file.
* basic.exp: Run fpu64-ps.s.
diff --git a/sim/testsuite/sim/mips/basic.exp b/sim/testsuite/sim/mips/basic.exp
index ac5d405b3b..6fb64be5dc 100644
--- a/sim/testsuite/sim/mips/basic.exp
+++ b/sim/testsuite/sim/mips/basic.exp
@@ -36,7 +36,10 @@ proc run_hilo_test {testfile models nops} {
# board really is a simulator (sim tests don't work on real HW).
if {[istarget mips*-elf] && [board_info target exists is_simulator]} {
- if {[istarget mipsisa64*-elf]} {
+ if {[istarget mipsisa64sb1*-elf]} {
+ set models "sb1"
+ set submodels "mips1 mips2 mips3 mips4 mips32 mips64"
+ } elseif {[istarget mipsisa64*-elf]} {
set models "mips32 mips64"
set submodels "mips1 mips2 mips3 mips4"
} elseif {[istarget mipsisa32*-elf]} {
@@ -64,4 +67,5 @@ if {[istarget mips*-elf] && [board_info target exists is_simulator]} {
run_hilo_test hilo-hazard-3.s $models 2
run_sim_test fpu64-ps.s $submodels
+ run_sim_test fpu64-ps-sb1.s $submodels
}
diff --git a/sim/testsuite/sim/mips/fpu64-ps-sb1.s b/sim/testsuite/sim/mips/fpu64-ps-sb1.s
new file mode 100644
index 0000000000..a39d0799c0
--- /dev/null
+++ b/sim/testsuite/sim/mips/fpu64-ps-sb1.s
@@ -0,0 +1,72 @@
+# mips test sanity, expected to pass.
+# mach: sb1
+# as: -mabi=eabi
+# ld: -N -Ttext=0x80010000
+# output: *\\npass\\n
+
+ .include "testutils.inc"
+
+ .macro check_ps psval, upperval, lowerval
+ .set push
+ .set noreorder
+ cvt.s.pu $f0, \psval # upper
+ cvt.s.pl $f2, \psval # lower
+ li.s $f4, \upperval
+ li.s $f6, \lowerval
+ c.eq.s $fcc0, $f0, $f4
+ bc1f $fcc0, _fail
+ c.eq.s $fcc0, $f2, $f6
+ bc1f $fcc0, _fail
+ nop
+ .set pop
+ .endm
+
+ setup
+
+ .set noreorder
+
+ .ent DIAG
+DIAG:
+
+ # make sure that Status.FR, .CU1, and .SBX are set.
+ mfc0 $2, $12
+ or $2, $2, (1 << 26) | (1 << 29) | (1 << 16)
+ mtc0 $2, $12
+
+
+ li.s $f10, 4.0
+ li.s $f12, 16.0
+ cvt.ps.s $f20, $f10, $f12 # $f20: u=4.0, l=16.0
+
+ li.s $f10, -1.0
+ li.s $f12, 2.0
+ cvt.ps.s $f22, $f10, $f12 # $f22: u=-1.0, l=2.0
+
+
+ writemsg "div.ps"
+
+ div.ps $f8, $f20, $f22
+ check_ps $f8, -4.0, 8.0
+
+
+ writemsg "recip.ps"
+
+ recip.ps $f8, $f20
+ check_ps $f8, 0.25, 0.0625
+
+
+ writemsg "rsqrt.ps"
+
+ rsqrt.ps $f8, $f20
+ check_ps $f8, 0.5, 0.25
+
+
+ writemsg "sqrt.ps"
+
+ sqrt.ps $f8, $f20
+ check_ps $f8, 2.0, 4.0
+
+
+ pass
+
+ .end DIAG
OpenPOWER on IntegriCloud