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authorFrank Ch. Eigler <fche@redhat.com>2000-03-02 18:12:44 +0000
committerFrank Ch. Eigler <fche@redhat.com>2000-03-02 18:12:44 +0000
commit58fddbac5a7cfd4404994be8d2a59dc8d72d7259 (patch)
tree48070796dc377b2d37bc0457edfa5662bed2975b /sim/testsuite
parent667620fa2734b3cadc8fa902caa1701fe2967197 (diff)
downloadppe42-binutils-58fddbac5a7cfd4404994be8d2a59dc8d72d7259.tar.gz
ppe42-binutils-58fddbac5a7cfd4404994be8d2a59dc8d72d7259.zip
* whitespace correction
Diffstat (limited to 'sim/testsuite')
-rw-r--r--sim/testsuite/ChangeLog4
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 5c537dc617..5edc5927a2 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -254,13 +254,11 @@ Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com>
* Makefile.in (RUNTEST): Fix path to runtest.
-
Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com>
* sim/m32r/unlock.cgs: Fixed test.
* sim/m32r/mvfc.cgs: Fixed test.
* sim/m32r/remu.cgs: Fixed test.
-
* sim/m32r/bnc24.cgs: Test long BNC instruction.
* sim/m32r/bnc8.cgs: Test short BNC instruction.
* sim/m32r/ld-plus.cgs: Test LD instruction.
@@ -278,6 +276,7 @@ Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com>
* sim/m32r/neg.cgs: Test NEG instruction.
* sim/m32r/not.cgs: Test NOT instruction.
* sim/m32r/unlock.cgs: Test UNLOCK instruction.
+
Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
* sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
@@ -324,6 +323,7 @@ Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
* sim/m32r/srli.cgs: Test SRLI instruction.
* sim/m32r/xor3.cgs: Test XOR3 instruction.
* sim/m32r/xor.cgs: Test XOR instruction.
+
Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
* config/default.exp: New file.
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