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authorChris Demetriou <cgd@google.com>2002-02-28 07:07:56 +0000
committerChris Demetriou <cgd@google.com>2002-02-28 07:07:56 +0000
commit3d81f391161e0680a8beeb441a09d3086640a738 (patch)
tree8e6be9c6c442a31dd24f7d302505817bcc783357 /sim/mips
parentaf5107af975bcf912be1187f4210706db408dabe (diff)
downloadppe42-binutils-3d81f391161e0680a8beeb441a09d3086640a738.tar.gz
ppe42-binutils-3d81f391161e0680a8beeb441a09d3086640a738.zip
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (PREFX): This is a 64-bit instruction, use '64' as the filter flag.
Diffstat (limited to 'sim/mips')
-rw-r--r--sim/mips/ChangeLog5
-rw-r--r--sim/mips/mips.igen2
2 files changed, 6 insertions, 1 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 4789ba900a..3581d5e9c9 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,5 +1,10 @@
2002-02-27 Chris Demetriou <cgd@broadcom.com>
+ * mips.igen (PREFX): This is a 64-bit instruction, use '64'
+ as the filter flag.
+
+2002-02-27 Chris Demetriou <cgd@broadcom.com>
+
* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
add a comma) so that it more closely match the MIPS ISA
documentation opcode partitioning.
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index d19ac97371..76b45e9ea8 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -3975,7 +3975,7 @@
}
-010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
+010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
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