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| author | Stephane Carrez <stcarrez@nerim.fr> | 2003-03-01 16:00:09 +0000 |
|---|---|---|
| committer | Stephane Carrez <stcarrez@nerim.fr> | 2003-03-01 16:00:09 +0000 |
| commit | 00416c6ed6b354207787df2ac7a6b1e8ad11fece (patch) | |
| tree | 7ff5a39cfcba5de551f0e15125b517a13e162765 /sim/m68hc11 | |
| parent | eadc1c87ebd3d01cb41b412ca7d436aba8fb67a3 (diff) | |
| download | ppe42-binutils-00416c6ed6b354207787df2ac7a6b1e8ad11fece.tar.gz ppe42-binutils-00416c6ed6b354207787df2ac7a6b1e8ad11fece.zip | |
* interp.c (sim_fetch_register): Only store a single byte for
1 byte registers.
Diffstat (limited to 'sim/m68hc11')
| -rw-r--r-- | sim/m68hc11/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/m68hc11/interp.c | 11 |
2 files changed, 14 insertions, 2 deletions
diff --git a/sim/m68hc11/ChangeLog b/sim/m68hc11/ChangeLog index 325b8874a7..21957ef779 100644 --- a/sim/m68hc11/ChangeLog +++ b/sim/m68hc11/ChangeLog @@ -1,3 +1,8 @@ +2003-03-01 Stephane Carrez <stcarrez@nerim.fr> + + * interp.c (sim_fetch_register): Only store a single byte for + 1 byte registers. + 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_prepare_for_program, sim_open) diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c index 8a60606223..3da382d88a 100644 --- a/sim/m68hc11/interp.c +++ b/sim/m68hc11/interp.c @@ -554,8 +554,15 @@ sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length) val = 0; break; } - memory[0] = val >> 8; - memory[1] = val & 0x0FF; + if (size == 1) + { + memory[0] = val; + } + else + { + memory[0] = val >> 8; + memory[1] = val & 0x0FF; + } return size; } |
