* compile.c: Change literal regnumbers to REGNUMS.

2 files changed, 19 insertions, 13 deletions

diff --git a/sim/h8300/ChangeLog b/sim/h8300/ChangeLog
index 63925e647d..c143fa1078 100644
--- a/sim/h8300/ChangeLog
+++ b/sim/h8300/ChangeLog
@@ -1,3 +1,8 @@
+2002-05-17  Andrey Volkov  (avolkov@transas.com)
+
+	* compile.c: Change literal regnumbers to REGNUMS. 
+	Fix instruction and cycles counting
+
 2001-12-20  Kazu Hirata  <kazu@hxi.com>
 
 	* compile.c: Fix formatting.
diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index 5e66dcb095..a698ee58b9 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -111,10 +111,7 @@ static int memory_size;
 static int
 get_now ()
 {
-#ifndef WIN32
-  return time (0);
-#endif
-  return 0;
+  return time (0);	/* WinXX HAS UNIX like 'time', so why not using it? */
 }
 
 static int
@@ -155,7 +152,7 @@ lvalue (x, rn)
       return X (OP_MEM, SP);
 
     default:
-      abort ();
+      abort (); /* ?? May be something more usefull? */
     }
 }
 
@@ -608,7 +605,7 @@ fetch (arg, n)
       return t;
 
     default:
-      abort ();
+      abort (); /* ?? May be something more usefull? */
 
     }
 }
@@ -997,8 +994,12 @@ sim_resume (sd, step, siggnal)
 
 #endif
 
-      cycles += code->cycles;
-      insts++;
+      if (code->opcode)
+       {
+        cycles += code->cycles;
+        insts++;
+       }
+
       switch (code->opcode)
 	{
 	case 0:
@@ -1860,10 +1861,10 @@ sim_fetch_register (sd, rn, buf, length)
     {
     default:
       abort ();
-    case 8:
+    case CCR_REGNUM:
       v = cpu.ccr;
       break;
-    case 9:
+    case PC_REGNUM:
       v = cpu.pc;
       break;
     case R0_REGNUM:
@@ -1876,15 +1877,15 @@ sim_fetch_register (sd, rn, buf, length)
     case R7_REGNUM:
       v = cpu.regs[rn];
       break;
-    case 10:
+    case CYCLE_REGNUM:
       v = cpu.cycles;
       longreg = 1;
       break;
-    case 11:
+    case TICK_REGNUM:
       v = cpu.ticks;
       longreg = 1;
       break;
-    case 12:
+    case INST_REGNUM:
       v = cpu.insts;
       longreg = 1;
       break;