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authorYufeng Zhang <yufeng.zhang@arm.com>2013-11-18 11:57:19 +0000
committerYufeng Zhang <yufeng.zhang@arm.com>2013-11-18 11:57:19 +0000
commitb31f4fea7757bad63c1061aabba19401a6b737e4 (patch)
treeeb2f8fd6bf83ef7ccf219f9a0b4bc634e5b755c2 /opcodes
parentac6cefb0a8168a4187161f0262b1e41c2d248a88 (diff)
downloadppe42-binutils-b31f4fea7757bad63c1061aabba19401a6b737e4.tar.gz
ppe42-binutils-b31f4fea7757bad63c1061aabba19401a6b737e4.zip
Revert "Add support for AArch64 trace unit registers."
This reverts commit 7568a4e05cc35bc96e7a422a7f3a453665479197.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog12
-rw-r--r--opcodes/aarch64-opc.c236
2 files changed, 12 insertions, 236 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8920253c9c..75532119ab 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ Revert
+
+ 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64-opc.c (CPENT): New define.
+ (F_READONLY, F_WRITEONLY): Likewise.
+ (aarch64_sys_regs): Add trace unit registers.
+ (aarch64_sys_reg_readonly_p): New function.
+ (aarch64_sys_reg_writeonly_p): Ditto.
+
2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-opc.c (CPENT): New define.
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 131e4d2094..af1472a582 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2676,8 +2676,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
/* for 3.9.10 System Instructions */
#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
-/* Trace unit registers. */
-#define CPENT(crn,crm,op2) CPENC(2,1,(crn),(crm),(op2))
#define C0 0
#define C1 1
@@ -2699,18 +2697,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
#ifdef F_DEPRECATED
#undef F_DEPRECATED
#endif
-
-#ifdef F_READONLY
-#undef F_READONLY
-#endif
-
-#ifdef F_WRITEONLY
-#undef F_WRITEONLY
-#endif
-
#define F_DEPRECATED 0x1 /* Deprecated system register. */
-#define F_READONLY 0x2 /* Not for MSR. */
-#define F_WRITEONLY 0x4 /* Not for MRS. */
/* TODO there are two more issues need to be resolved
1. handle read-only and write-only system registers
@@ -3023,217 +3010,6 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
{ "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
{ "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
- /* Trace unit registers. */
- { "trcprgctlr", CPENT(C0,C1,0), 0 },
- { "trcprocselr", CPENT(C0,C2,0), 0 },
- { "trcstatr", CPENT(C0,C3,0), F_READONLY },
- { "trcconfigr", CPENT(C0,C4,0), 0 },
- { "trcauxctlr", CPENT(C0,C6,0), 0 },
- { "trceventctl0r", CPENT(C0,C8,0), 0 },
- { "trceventctl1r", CPENT(C0,C9,0), 0 },
- { "trcstallctlr", CPENT(C0,C11,0), 0 },
- { "trctsctlr", CPENT(C0,C12,0), 0 },
- { "trcsyncpr", CPENT(C0,C13,0), 0 },
- { "trcccctlr", CPENT(C0,C14,0), 0 },
- { "trcbbctlr", CPENT(C0,C15,0), 0 },
- { "trctraceidr", CPENT(C0,C0,1), 0 },
- { "trcqctlr", CPENT(C0,C1,1), 0 },
- { "trcvictlr", CPENT(C0,C0,2), 0 },
- { "trcviiectlr", CPENT(C0,C1,2), 0 },
- { "trcvissctlr", CPENT(C0,C2,2), 0 },
- { "trcvipcssctlr", CPENT(C0,C3,2), 0 },
- { "trcvdctlr", CPENT(C0,C8,2), 0 },
- { "trcvdsacctlr", CPENT(C0,C9,2), 0 },
- { "trcvdarcctlr", CPENT(C0,C10,2), 0 },
- { "trcseqevr0", CPENT(C0,C0,4), 0 },
- { "trcseqevr1", CPENT(C0,C1,4), 0 },
- { "trcseqevr2", CPENT(C0,C2,4), 0 },
- { "trcseqrstevr", CPENT(C0,C6,4), 0 },
- { "trcseqstr", CPENT(C0,C7,4), 0 },
- { "trcextinselr", CPENT(C0,C8,4), 0 },
- { "trccntrldvr0", CPENT(C0,C0,5), 0 },
- { "trccntrldvr1", CPENT(C0,C1,5), 0 },
- { "trccntrldvr2", CPENT(C0,C2,5), 0 },
- { "trccntrldvr3", CPENT(C0,C3,5), 0 },
- { "trccntctlr0", CPENT(C0,C4,5), 0 },
- { "trccntctlr1", CPENT(C0,C5,5), 0 },
- { "trccntctlr2", CPENT(C0,C6,5), 0 },
- { "trccntctlr3", CPENT(C0,C7,5), 0 },
- { "trccntvr0", CPENT(C0,C8,5), 0 },
- { "trccntvr1", CPENT(C0,C9,5), 0 },
- { "trccntvr2", CPENT(C0,C10,5), 0 },
- { "trccntvr3", CPENT(C0,C11,5), 0 },
- { "trcidr8", CPENT(C0,C0,6), F_READONLY },
- { "trcidr9", CPENT(C0,C1,6), F_READONLY },
- { "trcidr10", CPENT(C0,C2,6), F_READONLY },
- { "trcidr11", CPENT(C0,C3,6), F_READONLY },
- { "trcidr12", CPENT(C0,C4,6), F_READONLY },
- { "trcidr13", CPENT(C0,C5,6), F_READONLY },
- { "trcimspec0", CPENT(C0,C0,7), 0 },
- { "trcimspec1", CPENT(C0,C1,7), 0 },
- { "trcimspec2", CPENT(C0,C2,7), 0 },
- { "trcimspec3", CPENT(C0,C3,7), 0 },
- { "trcimspec4", CPENT(C0,C4,7), 0 },
- { "trcimspec5", CPENT(C0,C5,7), 0 },
- { "trcimspec6", CPENT(C0,C6,7), 0 },
- { "trcimspec7", CPENT(C0,C7,7), 0 },
- { "trcidr0", CPENT(C0,C8,7), F_READONLY },
- { "trcidr1", CPENT(C0,C9,7), F_READONLY },
- { "trcidr2", CPENT(C0,C10,7), F_READONLY },
- { "trcidr3", CPENT(C0,C11,7), F_READONLY },
- { "trcidr4", CPENT(C0,C12,7), F_READONLY },
- { "trcidr5", CPENT(C0,C13,7), F_READONLY },
- { "trcidr6", CPENT(C0,C14,7), F_READONLY },
- { "trcidr7", CPENT(C0,C15,7), F_READONLY },
- { "trcrsctlr2", CPENT(C1,C2,0), 0 },
- { "trcrsctlr3", CPENT(C1,C3,0), 0 },
- { "trcrsctlr4", CPENT(C1,C4,0), 0 },
- { "trcrsctlr5", CPENT(C1,C5,0), 0 },
- { "trcrsctlr6", CPENT(C1,C6,0), 0 },
- { "trcrsctlr7", CPENT(C1,C7,0), 0 },
- { "trcrsctlr8", CPENT(C1,C8,0), 0 },
- { "trcrsctlr9", CPENT(C1,C9,0), 0 },
- { "trcrsctlr10", CPENT(C1,C10,0), 0 },
- { "trcrsctlr11", CPENT(C1,C11,0), 0 },
- { "trcrsctlr12", CPENT(C1,C12,0), 0 },
- { "trcrsctlr13", CPENT(C1,C13,0), 0 },
- { "trcrsctlr14", CPENT(C1,C14,0), 0 },
- { "trcrsctlr15", CPENT(C1,C15,0), 0 },
- { "trcrsctlr16", CPENT(C1,C0,1), 0 },
- { "trcrsctlr17", CPENT(C1,C1,1), 0 },
- { "trcrsctlr18", CPENT(C1,C2,1), 0 },
- { "trcrsctlr19", CPENT(C1,C3,1), 0 },
- { "trcrsctlr20", CPENT(C1,C4,1), 0 },
- { "trcrsctlr21", CPENT(C1,C5,1), 0 },
- { "trcrsctlr22", CPENT(C1,C6,1), 0 },
- { "trcrsctlr23", CPENT(C1,C7,1), 0 },
- { "trcrsctlr24", CPENT(C1,C8,1), 0 },
- { "trcrsctlr25", CPENT(C1,C9,1), 0 },
- { "trcrsctlr26", CPENT(C1,C10,1), 0 },
- { "trcrsctlr27", CPENT(C1,C11,1), 0 },
- { "trcrsctlr28", CPENT(C1,C12,1), 0 },
- { "trcrsctlr29", CPENT(C1,C13,1), 0 },
- { "trcrsctlr30", CPENT(C1,C14,1), 0 },
- { "trcrsctlr31", CPENT(C1,C15,1), 0 },
- { "trcssccr0", CPENT(C1,C0,2), 0 },
- { "trcssccr1", CPENT(C1,C1,2), 0 },
- { "trcssccr2", CPENT(C1,C2,2), 0 },
- { "trcssccr3", CPENT(C1,C3,2), 0 },
- { "trcssccr4", CPENT(C1,C4,2), 0 },
- { "trcssccr5", CPENT(C1,C5,2), 0 },
- { "trcssccr6", CPENT(C1,C6,2), 0 },
- { "trcssccr7", CPENT(C1,C7,2), 0 },
- { "trcsscsr0", CPENT(C1,C8,2), 0 },
- { "trcsscsr1", CPENT(C1,C9,2), 0 },
- { "trcsscsr2", CPENT(C1,C10,2), 0 },
- { "trcsscsr3", CPENT(C1,C11,2), 0 },
- { "trcsscsr4", CPENT(C1,C12,2), 0 },
- { "trcsscsr5", CPENT(C1,C13,2), 0 },
- { "trcsscsr6", CPENT(C1,C14,2), 0 },
- { "trcsscsr7", CPENT(C1,C15,2), 0 },
- { "trcsspcicr0", CPENT(C1,C0,3), 0 },
- { "trcsspcicr1", CPENT(C1,C1,3), 0 },
- { "trcsspcicr2", CPENT(C1,C2,3), 0 },
- { "trcsspcicr3", CPENT(C1,C3,3), 0 },
- { "trcsspcicr4", CPENT(C1,C4,3), 0 },
- { "trcsspcicr5", CPENT(C1,C5,3), 0 },
- { "trcsspcicr6", CPENT(C1,C6,3), 0 },
- { "trcsspcicr7", CPENT(C1,C7,3), 0 },
- { "trcoslar", CPENT(C1,C0,4), F_WRITEONLY },
- { "trcoslsr", CPENT(C1,C1,4), F_READONLY },
- { "trcpdcr", CPENT(C1,C4,4), 0 },
- { "trcpdsr", CPENT(C1,C5,4), F_READONLY },
- { "trcacvr0", CPENT(C2,C0,0), 0 },
- { "trcacvr1", CPENT(C2,C2,0), 0 },
- { "trcacvr2", CPENT(C2,C4,0), 0 },
- { "trcacvr3", CPENT(C2,C6,0), 0 },
- { "trcacvr4", CPENT(C2,C8,0), 0 },
- { "trcacvr5", CPENT(C2,C10,0), 0 },
- { "trcacvr6", CPENT(C2,C12,0), 0 },
- { "trcacvr7", CPENT(C2,C14,0), 0 },
- { "trcacvr8", CPENT(C2,C0,1), 0 },
- { "trcacvr9", CPENT(C2,C2,1), 0 },
- { "trcacvr10", CPENT(C2,C4,1), 0 },
- { "trcacvr11", CPENT(C2,C6,1), 0 },
- { "trcacvr12", CPENT(C2,C8,1), 0 },
- { "trcacvr13", CPENT(C2,C10,1), 0 },
- { "trcacvr14", CPENT(C2,C12,1), 0 },
- { "trcacvr15", CPENT(C2,C14,1), 0 },
- { "trcacatr0", CPENT(C2,C0,2), 0 },
- { "trcacatr1", CPENT(C2,C2,2), 0 },
- { "trcacatr2", CPENT(C2,C4,2), 0 },
- { "trcacatr3", CPENT(C2,C6,2), 0 },
- { "trcacatr4", CPENT(C2,C8,2), 0 },
- { "trcacatr5", CPENT(C2,C10,2), 0 },
- { "trcacatr6", CPENT(C2,C12,2), 0 },
- { "trcacatr7", CPENT(C2,C14,2), 0 },
- { "trcacatr8", CPENT(C2,C0,3), 0 },
- { "trcacatr9", CPENT(C2,C2,3), 0 },
- { "trcacatr10", CPENT(C2,C4,3), 0 },
- { "trcacatr11", CPENT(C2,C6,3), 0 },
- { "trcacatr12", CPENT(C2,C8,3), 0 },
- { "trcacatr13", CPENT(C2,C10,3), 0 },
- { "trcacatr14", CPENT(C2,C12,3), 0 },
- { "trcacatr15", CPENT(C2,C14,3), 0 },
- { "trcdvcvr0", CPENT(C2,C0,4), 0 },
- { "trcdvcvr1", CPENT(C2,C4,4), 0 },
- { "trcdvcvr2", CPENT(C2,C8,4), 0 },
- { "trcdvcvr3", CPENT(C2,C12,4), 0 },
- { "trcdvcvr4", CPENT(C2,C0,5), 0 },
- { "trcdvcvr5", CPENT(C2,C4,5), 0 },
- { "trcdvcvr6", CPENT(C2,C8,5), 0 },
- { "trcdvcvr7", CPENT(C2,C12,5), 0 },
- { "trcdvcmr0", CPENT(C2,C0,6), 0 },
- { "trcdvcmr1", CPENT(C2,C4,6), 0 },
- { "trcdvcmr2", CPENT(C2,C8,6), 0 },
- { "trcdvcmr3", CPENT(C2,C12,6), 0 },
- { "trcdvcmr4", CPENT(C2,C0,7), 0 },
- { "trcdvcmr5", CPENT(C2,C4,7), 0 },
- { "trcdvcmr6", CPENT(C2,C8,7), 0 },
- { "trcdvcmr7", CPENT(C2,C12,7), 0 },
- { "trccidcvr0", CPENT(C3,C0,0), 0 },
- { "trccidcvr1", CPENT(C3,C2,0), 0 },
- { "trccidcvr2", CPENT(C3,C4,0), 0 },
- { "trccidcvr3", CPENT(C3,C6,0), 0 },
- { "trccidcvr4", CPENT(C3,C8,0), 0 },
- { "trccidcvr5", CPENT(C3,C10,0), 0 },
- { "trccidcvr6", CPENT(C3,C12,0), 0 },
- { "trccidcvr7", CPENT(C3,C14,0), 0 },
- { "trcvmidcvr0", CPENT(C3,C0,1), 0 },
- { "trcvmidcvr1", CPENT(C3,C2,1), 0 },
- { "trcvmidcvr2", CPENT(C3,C4,1), 0 },
- { "trcvmidcvr3", CPENT(C3,C6,1), 0 },
- { "trcvmidcvr4", CPENT(C3,C8,1), 0 },
- { "trcvmidcvr5", CPENT(C3,C10,1), 0 },
- { "trcvmidcvr6", CPENT(C3,C12,1), 0 },
- { "trcvmidcvr7", CPENT(C3,C14,1), 0 },
- { "trccidcctlr0", CPENT(C3,C0,2), 0 },
- { "trccidcctlr1", CPENT(C3,C1,2), 0 },
- { "trcvmidcctlr0", CPENT(C3,C2,2), 0 },
- { "trcvmidcctlr1", CPENT(C3,C3,2), 0 },
- { "trcitctrl", CPENT(C7,C0,4), 0 },
- { "trcclaimset", CPENT(C7,C8,6), 0 },
- { "trcclaimclr", CPENT(C7,C9,6), 0 },
- { "trcdevaff0", CPENT(C7,C10,6), F_READONLY },
- { "trcdevaff1", CPENT(C7,C11,6), F_READONLY },
- { "trclar", CPENT(C7,C12,6), F_WRITEONLY },
- { "trclsr", CPENT(C7,C13,6), F_READONLY },
- { "trcauthstatus", CPENT(C7,C14,6), F_READONLY },
- { "trcdevarch", CPENT(C7,C15,6), F_READONLY },
- { "trcdevid", CPENT(C7,C2,7), F_READONLY },
- { "trcdevtype", CPENT(C7,C3,7), F_READONLY },
- { "trcpidr4", CPENT(C7,C4,7), F_READONLY },
- { "trcpidr5", CPENT(C7,C5,7), F_READONLY },
- { "trcpidr6", CPENT(C7,C6,7), F_READONLY },
- { "trcpidr7", CPENT(C7,C7,7), F_READONLY },
- { "trcpidr0", CPENT(C7,C8,7), F_READONLY },
- { "trcpidr1", CPENT(C7,C9,7), F_READONLY },
- { "trcpidr2", CPENT(C7,C10,7), F_READONLY },
- { "trcpidr3", CPENT(C7,C11,7), F_READONLY },
- { "trccidr0", CPENT(C7,C12,7), F_READONLY },
- { "trccidr1", CPENT(C7,C13,7), F_READONLY },
- { "trccidr2", CPENT(C7,C14,7), F_READONLY },
- { "trccidr3", CPENT(C7,C15,7), F_READONLY },
{ 0, CPENC(0,0,0,0,0), 0 },
};
@@ -3243,18 +3019,6 @@ aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
return (reg->flags & F_DEPRECATED) != 0;
}
-bfd_boolean
-aarch64_sys_reg_readonly_p (const aarch64_sys_reg *reg)
-{
- return (reg->flags & F_READONLY) != 0;
-}
-
-bfd_boolean
-aarch64_sys_reg_writeonly_p (const aarch64_sys_reg *reg)
-{
- return (reg->flags & F_WRITEONLY) != 0;
-}
-
const struct aarch64_name_value_pair aarch64_pstatefields [] =
{
{ "spsel", 0x05 },
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