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| author | David S. Miller <davem@redhat.com> | 2012-04-27 20:43:35 +0000 |
|---|---|---|
| committer | David S. Miller <davem@redhat.com> | 2012-04-27 20:43:35 +0000 |
| commit | 2e52845baf0090fef75f46b7619935f166ad063d (patch) | |
| tree | 4c5d31dd1bb967faff1c0df56ca3168ec84cc2cb /opcodes | |
| parent | 22d2b532b8f2de5bd20d70b89a06894a5b9f97b1 (diff) | |
| download | ppe42-binutils-2e52845baf0090fef75f46b7619935f166ad063d.tar.gz ppe42-binutils-2e52845baf0090fef75f46b7619935f166ad063d.zip | |
Add support for sparc %cfr ASR register.
opcodes/
* sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
* sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
gas/
* config/tc-sparc.c (v9a_asr_table): Add 'cfr'.
gas/testsuite/
* gas/sparc/sparc.exp: Run cfr test.
* gas/sparc/cfr.s: New testcase.
* gas/sparc/cfr.d: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 3 | ||||
| -rw-r--r-- | opcodes/sparc-dis.c | 2 | ||||
| -rw-r--r-- | opcodes/sparc-opc.c | 3 |
3 files changed, 7 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 43f4a9d48c..f857091609 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,8 @@ 2012-04-27 David S. Miller <davem@davemloft.net> + * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'. + * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr. + * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'. * sparc-dis.c (v9a_asr_reg_names): Add 'pause'. diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c index 7599f890da..b0899a69ae 100644 --- a/opcodes/sparc-dis.c +++ b/opcodes/sparc-dis.c @@ -108,7 +108,7 @@ static char *v9_hpriv_reg_names[] = static char *v9a_asr_reg_names[] = { "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", - "softint", "tick_cmpr", "stick", "stick_cmpr", "resv26", + "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr", "pause", "cps" }; diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c index 1f9ee49f98..cf00a8976e 100644 --- a/opcodes/sparc-opc.c +++ b/opcodes/sparc-opc.c @@ -876,6 +876,8 @@ const struct sparc_opcode sparc_opcodes[] = { { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick */ { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick_cmpr */ { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick_cmpr */ +{ "wr", F3(2, 0x30, 0)|RD(26), F3(~2, ~0x30, ~0)|RD(~26)|ASI(~0), "1,2,_", 0, HWCAP_CBCOND, v9b }, /* wr r,r,%cfr */ +{ "wr", F3(2, 0x30, 1)|RD(26), F3(~2, ~0x30, ~1)|RD(~26), "1,i,_", 0, HWCAP_CBCOND, v9b }, /* wr r,i,%cfr */ { "wr", F3(2, 0x30, 0)|RD(27), F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0), "1,2,_", 0, HWCAP_PAUSE, v9b }, /* wr r,r,%pause */ { "wr", F3(2, 0x30, 1)|RD(27), F3(~2, ~0x30, ~1)|RD(~27), "1,i,_", 0, HWCAP_PAUSE, v9b }, /* wr r,i,%pause */ { "wr", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, HWCAP_VIS3, v9b }, /* wr r,r,%cps */ @@ -903,6 +905,7 @@ const struct sparc_opcode sparc_opcodes[] = { { "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %tick_cmpr,r */ { "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick,r */ { "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick_cmpr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(26), F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0), "/,d", HWCAP_CBCOND, 0, v9b }, /* rd %cfr,r */ { "rd", F3(2, 0x28, 0)|RS1(28), F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0), "/,d", 0, HWCAP_VIS3, v9b }, /* rd %cps,r */ { "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, 0, v9 }, /* rdpr %priv,r */ |
