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| author | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2003-03-21 13:28:09 +0000 |
|---|---|---|
| committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2003-03-21 13:28:09 +0000 |
| commit | af169f23335a1df5cf6e27b1f3087c18ae32e5a7 (patch) | |
| tree | 9bc014f844d4549181d46f207cdf244a726dcc91 /opcodes/s390-opc.c | |
| parent | 1bd490c46b5a3d1313f60553d9a7d4c329bd26e9 (diff) | |
| download | ppe42-binutils-af169f23335a1df5cf6e27b1f3087c18ae32e5a7.tar.gz ppe42-binutils-af169f23335a1df5cf6e27b1f3087c18ae32e5a7.zip | |
* s390-dis.c (init_disasm): Rename S390_OPCODE_ESAME to
S390_OPCODE_ZARCH.
(print_insn_s390): Use new modes field of s390_opcodes.
* s390-mkopc.c (ARCHBITS_ESAONLY, ARCHBITS_ESA, ARCHBITS_ESAME): Remove.
(s390_opcode_mode_val, s390_opcode_cpu_val): New enums.
(struct op_struct): Remove archbits. Add mode_bits and min_cpu.
(insertOpcode): Replace archbits by min_cpu and mode_bits.
(dumpTable): Write mode_bits and min_cpu instead of archbits.
(main): Adapt to new format in s390-opcode.txt.
* s390-opc.c (s390_opformats): Replace archbits by min_cpu and
mode_bits.
* s390-opc.txt: Replace archbits by min_cpu and mode_bits.
Diffstat (limited to 'opcodes/s390-opc.c')
| -rw-r--r-- | opcodes/s390-opc.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 7cd8231d95..a2837833d7 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -293,23 +293,23 @@ const struct s390_operand s390_operands[] = const struct s390_opcode s390_opformats[] = { - { "e", OP8(0x00LL), MASK_E, INSTR_E, 3 }, - { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3 }, - { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3 }, - { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3 }, - { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3 }, - { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3 }, - { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3 }, - { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3 }, - { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3 }, - { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3 }, - { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3 }, - { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3 }, - { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3 }, - { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3 }, - { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3 }, - { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3 }, - { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3 }, + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, }; const int s390_num_opformats = |
