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| author | H.J. Lu <hjl.tools@gmail.com> | 2008-02-23 17:29:17 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2008-02-23 17:29:17 +0000 |
| commit | 849830bdfb30c93fda1fd4098b7070e8159d3663 (patch) | |
| tree | b88c05e367d6766b332cdcd12786e6b8e4cc1be3 /opcodes/i386-opc.tbl | |
| parent | 1cd81501f406fd8c488574d3130c61ab4c492315 (diff) | |
| download | ppe42-binutils-849830bdfb30c93fda1fd4098b7070e8159d3663.tar.gz ppe42-binutils-849830bdfb30c93fda1fd4098b7070e8159d3663.zip | |
gas/testsuite/
2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/jump.s: Add tests for far branches.
* gas/i386/jump16.s: Likewise.
* gas/i386/jump.d: Updated.
* gas/i386/jump16.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
* gas/i386/x86-64-inval.s: Add tests for 16-bit near indirect
branches.
opcodes/
2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Disallow 16-bit near indirect branches for
x86-64.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index cfb31f1b2a..2fec30aab0 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -318,7 +318,7 @@ shrd, 2, 0xfad, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|R call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32 } call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Disp16|Disp32 } call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute } -call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute } +call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute } // Intel Syntax call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } // Intel Syntax @@ -328,7 +328,7 @@ lcall, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { jmp, 1, 0xeb, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute } -jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute } +jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute } // Intel Syntax. jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } // Intel Syntax. |
