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authorJan Hubicka <jh@suse.cz>2001-01-13 09:05:55 +0000
committerJan Hubicka <jh@suse.cz>2001-01-13 09:05:55 +0000
commite2914f484eed1dc5a9abd52301dae35f7500ff48 (patch)
tree219463cfd50346692bb759efd223bdfd6c2fb8ad /include
parent272d76e0cbba693781509c939ddfda5941a50e9d (diff)
downloadppe42-binutils-e2914f484eed1dc5a9abd52301dae35f7500ff48.tar.gz
ppe42-binutils-e2914f484eed1dc5a9abd52301dae35f7500ff48.zip
* i386.c (md_assemble): Check cpu_flags even for nullary instructions.
* i386.h (i386_optab): Fix pusha and ret templates. * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret templates.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ChangeLog4
-rw-r--r--include/opcode/i386.h8
2 files changed, 9 insertions, 3 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index b506b66af1..4632f75208 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz>
+
+ * i386.h (i386_optab): Fix pusha and ret templates.
+
2001-01-11 Peter Targett <peter.targett@arccores.com>
* arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index d095e5baab..f6f7afd90c 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -154,7 +154,7 @@ static const template i386_optab[] = {
{"push", 1, 0x06, X, Cpu64, q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
{"push", 1, 0x0fa0, X, Cpu386|Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
-{"pusha", 0, 0x60, X, Cpu186|Cpu64, wl_Suf|DefaultSize, { 0, 0, 0 } },
+{"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } },
/* Pop instructions. */
{"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
@@ -389,8 +389,10 @@ static const template i386_optab[] = {
{"ljmp", 1, 0xff, 5, CpuNo64, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
{"ljmp", 1, 0xff, 5, Cpu64, q_Suf|Modrm|NoRex64, { WordMem|JumpAbsolute, 0, 0} },
-{"ret", 0, 0xc3, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
-{"ret", 1, 0xc2, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} },
+{"ret", 0, 0xc3, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} },
+{"ret", 1, 0xc2, X, CpuNo64,wlq_Suf|DefaultSize, { Imm16, 0, 0} },
+{"ret", 0, 0xc3, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"ret", 1, 0xc2, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },
{"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
{"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} },
{"enter", 2, 0xc8, X, Cpu186, wlq_Suf|DefaultSize, { Imm16, Imm8, 0} },
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