* config/tc-arm.c (parse_operands): Encode APSR_nzcv as r15.

        (do_vmrs): New function.
        (do_vmsr): New function.
        (insns): Add vmrs and vmsr.

        * gas/arm/vfp1xD.s: Add vmrs and vmsr instructions.
        * gas/arm/vfp1xD.d: Update expected disassembly.

5 files changed, 122 insertions, 3 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 94dc620df6..531b25caaf 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2009-11-16  Viktor Kutuzov  <vkutuzov@accesssoftek.com>
+
+	* config/tc-arm.c (parse_operands): Encode APSR_nzcv as r15.
+	(do_vmrs): New function.
+	(do_vmsr): New function.
+	(insns): Add vmrs and vmsr.
+
 2009-11-13  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/tc-i386.c (md_assemble): Check destination operand
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index aee851684f..9dbff11d9e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6303,6 +6303,8 @@ parse_operands (char *str, const unsigned char *pattern)
               if (found != 15)
                 goto failure;
               inst.operands[i].isvec = 1;
+	      /* APSR_nzcv is encoded in instructions as if it were the REG_PC.  */
+	      inst.operands[i].reg = REG_PC;
             }
           else
             goto failure;
@@ -7615,6 +7617,49 @@ do_vfp_nsyn_msr (void)
 }
 
 static void
+do_vmrs (void)
+{
+  unsigned Rt = inst.operands[0].reg;
+  
+  if (thumb_mode && inst.operands[0].reg == REG_SP)
+    {
+      inst.error = BAD_SP;
+      return;
+    }
+
+  /* APSR_ sets isvec. All other refs to PC are illegal.  */
+  if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
+    {
+      inst.error = BAD_PC;
+      return;
+    }
+
+  if (inst.operands[1].reg != 1)
+    first_error (_("operand 1 must be FPSCR"));
+
+  inst.instruction |= (Rt << 12);
+}
+
+static void
+do_vmsr (void)
+{
+  unsigned Rt = inst.operands[1].reg;
+  
+  if (thumb_mode)
+    reject_bad_reg (Rt);
+  else if (Rt == REG_PC)
+    {
+      inst.error = BAD_PC;
+      return;
+    }
+
+  if (inst.operands[0].reg != 1)
+    first_error (_("operand 0 must be FPSCR"));
+
+  inst.instruction |= (Rt << 12);
+}
+
+static void
 do_mrs (void)
 {
   if (do_vfp_nsyn_mrs () == SUCCESS)
@@ -17168,6 +17213,8 @@ static const struct asm_opcode insns[] =
  cCE("fmrs",	e100a10, 2, (RR, RVS),	      vfp_reg_from_sp),
  cCE("fmsr",	e000a10, 2, (RVS, RR),	      vfp_sp_from_reg),
  cCE("fmstat",	ef1fa10, 0, (),		      noargs),
+ cCE("vmrs",	ef10a10, 2, (APSR_RR, RVC),   vmrs),
+ cCE("vmsr",	ee10a10, 2, (RVC, RR),        vmsr),
  cCE("fsitos",	eb80ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
  cCE("fuitos",	eb80a40, 2, (RVS, RVS),	      vfp_sp_monadic),
  cCE("ftosis",	ebd0a40, 2, (RVS, RVS),	      vfp_sp_monadic),
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 165266d9b2..8426880469 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2009-11-16  Viktor Kutuzov  <vkutuzov@accesssoftek.com>
+
+	* gas/arm/vfp1xD.s: Add vmrs and vmsr instructions.
+	* gas/arm/vfp1xD.d: Update expected disassembly.
+
 2009-11-13  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/lock-1-intel.d: Updated.
diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d
index 8de7dd4a0e..eebc72bdae 100644
--- a/gas/testsuite/gas/arm/vfp1xD.d
+++ b/gas/testsuite/gas/arm/vfp1xD.d
@@ -249,5 +249,34 @@ Disassembly of section .text:
 0+3bc <[^>]*> eee70a10 	(vmsr|fmxr)	mvfr0, r0
 0+3c0 <[^>]*> eee60a10 	(vmsr|fmxr)	mvfr1, r0
 0+3c4 <[^>]*> eeec0a10 	(vmsr|fmxr)	<impl def 0xc>, r0
-0+3c8 <[^>]*> e1a00000 	nop			; \(mov r0, r0\)
-0+3cc <[^>]*> e1a00000 	nop			; \(mov r0, r0\)
+0+3c8 <[^>]*> eef10a10 	vmrs	r0, fpscr
+0+3cc <[^>]*> eef11a10 	vmrs	r1, fpscr
+0+3d0 <[^>]*> eef12a10 	vmrs	r2, fpscr
+0+3d4 <[^>]*> eef13a10 	vmrs	r3, fpscr
+0+3d8 <[^>]*> eef14a10 	vmrs	r4, fpscr
+0+3dc <[^>]*> eef15a10 	vmrs	r5, fpscr
+0+3e0 <[^>]*> eef16a10 	vmrs	r6, fpscr
+0+3e4 <[^>]*> eef17a10 	vmrs	r7, fpscr
+0+3e8 <[^>]*> eef18a10 	vmrs	r8, fpscr
+0+3ec <[^>]*> eef19a10 	vmrs	r9, fpscr
+0+3f0 <[^>]*> eef1aa10 	vmrs	sl, fpscr
+0+3f4 <[^>]*> eef1ba10 	vmrs	fp, fpscr
+0+3f8 <[^>]*> eef1ca10 	vmrs	ip, fpscr
+0+3fc <[^>]*> eef1ea10 	vmrs	lr, fpscr
+0+400 <[^>]*> eef1fa10 	vmrs	APSR_nzcv, fpscr
+0+404 <[^>]*> eee10a10 	vmsr	fpscr, r0
+0+408 <[^>]*> eee11a10 	vmsr	fpscr, r1
+0+40c <[^>]*> eee12a10 	vmsr	fpscr, r2
+0+410 <[^>]*> eee13a10 	vmsr	fpscr, r3
+0+414 <[^>]*> eee14a10 	vmsr	fpscr, r4
+0+418 <[^>]*> eee15a10 	vmsr	fpscr, r5
+0+41c <[^>]*> eee16a10 	vmsr	fpscr, r6
+0+420 <[^>]*> eee17a10 	vmsr	fpscr, r7
+0+424 <[^>]*> eee18a10 	vmsr	fpscr, r8
+0+428 <[^>]*> eee19a10 	vmsr	fpscr, r9
+0+42c <[^>]*> eee1aa10 	vmsr	fpscr, sl
+0+430 <[^>]*> eee1ba10 	vmsr	fpscr, fp
+0+434 <[^>]*> eee1ca10 	vmsr	fpscr, ip
+0+438 <[^>]*> eee1ea10 	vmsr	fpscr, lr
+0+43c <[^>]*> e1a00000 	nop			; \(mov r0, r0\)
+
diff --git a/gas/testsuite/gas/arm/vfp1xD.s b/gas/testsuite/gas/arm/vfp1xD.s
index ecc0226381..274a0b1ebc 100644
--- a/gas/testsuite/gas/arm/vfp1xD.s
+++ b/gas/testsuite/gas/arm/vfp1xD.s
@@ -349,5 +349,36 @@ F:
 	fmxr	mvfr1, r0
 	fmxr	c12, r0
 
-	nop
+	@ ARM VMSR/VMRS instructions
+	vmrs	r0, FPSCR
+	vmrs	r1, FPSCR
+	vmrs	r2, FPSCR
+	vmrs	r3, FPSCR
+	vmrs	r4, FPSCR
+	vmrs	r5, FPSCR
+	vmrs	r6, FPSCR
+	vmrs	r7, FPSCR
+	vmrs	r8, FPSCR
+	vmrs	r9, FPSCR
+	vmrs	r10, FPSCR
+	vmrs	r11, FPSCR
+	vmrs	r12, FPSCR
+	vmrs	r14, FPSCR
+	vmrs	APSR_nzcv, FPSCR
+
+	vmsr	FPSCR, r0
+	vmsr	FPSCR, r1
+	vmsr	FPSCR, r2
+	vmsr	FPSCR, r3
+	vmsr	FPSCR, r4
+	vmsr	FPSCR, r5
+	vmsr	FPSCR, r6
+	vmsr	FPSCR, r7
+	vmsr	FPSCR, r8
+	vmsr	FPSCR, r9
+	vmsr	FPSCR, r10
+	vmsr	FPSCR, r11
+	vmsr	FPSCR, r12
+	vmsr	FPSCR, r14
+
 	nop