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authorPaul Brook <paul@codesourcery.com>2004-01-09 11:53:16 +0000
committerPaul Brook <paul@codesourcery.com>2004-01-09 11:53:16 +0000
commite45d06306f80add6fd1b118833c03a46ee004872 (patch)
treef67d21e3d7f855eab77ce631893a6b80907253da /gas
parent041ab88cf047ecfa2c5c7421ab3976c9dcb6646a (diff)
downloadppe42-binutils-e45d06306f80add6fd1b118833c03a46ee004872.tar.gz
ppe42-binutils-e45d06306f80add6fd1b118833c03a46ee004872.zip
* gas/config/tc-arm.c (do_vfp_reg2_from_sp2): Rename from
do_vfp_sp_reg2. (do_vfp_sp2_from_reg2): New function. (insns): Use them. (do_vfp_dp_from_reg2): Check return values properly. * opcodes/arm-opc.h (arm_opcodes): Move generic mcrr after known specific opcodes. * gas/testsuite/gas/arm/vfp2.s, gas/arm/vfp2.d: New test. * gas/testsuite/gas/arm/arm.exp: Add them.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog7
-rw-r--r--gas/config/tc-arm.c43
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/arm/arm.exp2
-rw-r--r--gas/testsuite/gas/arm/vfp2.d17
-rw-r--r--gas/testsuite/gas/arm/vfp2.s18
6 files changed, 83 insertions, 9 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index e9efaf2b4d..1f0aa97caf 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2004-01-09 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (do_vfp_reg2_from_sp2): Rename from do_vfp_sp_reg2.
+ (do_vfp_sp2_from_reg2): New function.
+ (insns): Use them.
+ (do_vfp_dp_from_reg2): Check return values properly.
+
2004-01-08 Ian Lance Taylor <ian@wasabisystems.com>
* config/tc-mips.c (warn_nops): Remove static variable.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 74e1537f41..c290a92850 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -929,7 +929,8 @@ static void do_vfp_sp_dyadic PARAMS ((char *));
static void do_vfp_dp_dyadic PARAMS ((char *));
static void do_vfp_reg_from_sp PARAMS ((char *));
static void do_vfp_sp_from_reg PARAMS ((char *));
-static void do_vfp_sp_reg2 PARAMS ((char *));
+static void do_vfp_reg2_from_sp2 PARAMS ((char *));
+static void do_vfp_sp2_from_reg2 PARAMS ((char *));
static void do_vfp_reg_from_dp PARAMS ((char *));
static void do_vfp_reg2_from_dp PARAMS ((char *));
static void do_vfp_dp_from_reg PARAMS ((char *));
@@ -1976,8 +1977,8 @@ static const struct asm_opcode insns[] =
{"fcmpezd", 0xeeb50bc0, 7, FPU_VFP_EXT_V1, do_vfp_dp_compare_z},
/* VFP V2. */
- {"fmsrr", 0xec400a10, 5, FPU_VFP_EXT_V2, do_vfp_sp_reg2},
- {"fmrrs", 0xec500a10, 5, FPU_VFP_EXT_V2, do_vfp_sp_reg2},
+ {"fmsrr", 0xec400a10, 5, FPU_VFP_EXT_V2, do_vfp_sp2_from_reg2},
+ {"fmrrs", 0xec500a10, 5, FPU_VFP_EXT_V2, do_vfp_reg2_from_sp2},
{"fmdrr", 0xec400b10, 5, FPU_VFP_EXT_V2, do_vfp_dp_from_reg2},
{"fmrrd", 0xec500b10, 5, FPU_VFP_EXT_V2, do_vfp_reg2_from_dp},
@@ -8954,15 +8955,13 @@ do_vfp_reg_from_sp (str)
}
static void
-do_vfp_sp_reg2 (str)
+do_vfp_reg2_from_sp2 (str)
char *str;
{
skip_whitespace (str);
- if (reg_required_here (&str, 12) == FAIL)
- return;
-
- if (skip_past_comma (&str) == FAIL
+ if (reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
|| reg_required_here (&str, 16) == FAIL
|| skip_past_comma (&str) == FAIL)
{
@@ -9002,6 +9001,32 @@ do_vfp_sp_from_reg (str)
}
static void
+do_vfp_sp2_from_reg2 (str)
+ char *str;
+{
+ skip_whitespace (str);
+
+ /* We require exactly two consecutive SP registers. */
+ if (vfp_sp_reg_list (&str, VFP_REG_Sm) != 2)
+ {
+ if (! inst.error)
+ inst.error = _("only two consecutive VFP SP registers allowed here");
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 16) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ end_of_line (str);
+}
+
+static void
do_vfp_reg_from_dp (str)
char *str;
{
@@ -9075,7 +9100,7 @@ do_vfp_dp_from_reg2 (str)
if (skip_past_comma (&str) == FAIL
|| reg_required_here (&str, 12) == FAIL
|| skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 16))
+ || reg_required_here (&str, 16) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0e0ba9be71..24d56e144b 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2004-01-09 Paul Brook <paul@codesourcery.com>
+
+ * gas/arm/vfp2.s, gas/arm/vfp2.d: New test.
+ * gas/arm/arm.exp: Add them.
+
2004-01-08 Ian Lance Taylor <ian@wasabisystems.com>
* gas/mips/ldstla-n64.d: Pass -64 to assembler, not -n64.
diff --git a/gas/testsuite/gas/arm/arm.exp b/gas/testsuite/gas/arm/arm.exp
index 9eef1b3de2..9816497bd4 100644
--- a/gas/testsuite/gas/arm/arm.exp
+++ b/gas/testsuite/gas/arm/arm.exp
@@ -61,6 +61,8 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
run_dump_test "vfp1"
+ run_dump_test "vfp2"
+
run_errors_test "vfp-bad" "-mfpu=vfp" "VFP errors"
run_dump_test "xscale"
diff --git a/gas/testsuite/gas/arm/vfp2.d b/gas/testsuite/gas/arm/vfp2.d
new file mode 100644
index 0000000000..f9b6096081
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp2.d
@@ -0,0 +1,17 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: VFP Additional instructions
+#as: -mfpu=vfp
+
+# Test the ARM VFP Double Precision instructions
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> ec4a5b10 fmdrr d0, r5, sl
+0+004 <[^>]*> ec5a5b10 fmrrd r5, sl, d0
+0+008 <[^>]*> ec4a5a37 fmsrr r5, sl, {s15, s16}
+0+00c <[^>]*> ec5a5a37 fmrrs r5, sl, {s15, s16}
+0+010 <[^>]*> ec45ab1f fmdrr d15, sl, r5
+0+014 <[^>]*> ec55ab1f fmrrd sl, r5, d15
+0+018 <[^>]*> ec45aa38 fmsrr sl, r5, {s17, s18}
+0+01c <[^>]*> ec55aa38 fmrrs sl, r5, {s17, s18}
diff --git a/gas/testsuite/gas/arm/vfp2.s b/gas/testsuite/gas/arm/vfp2.s
new file mode 100644
index 0000000000..8a293abbd8
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp2.s
@@ -0,0 +1,18 @@
+@ VFP2 Additional instructions
+ .text
+ .global F
+F:
+ @ First we test the basic syntax and bit patterns of the opcodes.
+ @ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise
+ @ the full register bitpatterns
+
+ fmdrr d0, r5, r10
+ fmrrd r5, r10, d0
+ fmsrr {s15, s16}, r5, r10
+ fmrrs r5, r10, {s15, s16}
+
+ fmdrr d15, r10, r5
+ fmrrd r10, r5, d15
+ fmsrr {s17, s18}, r10, r5
+ fmrrs r10, r5, {s17, s18}
+
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