diff options
| author | Chris Demetriou <cgd@google.com> | 2003-04-02 18:43:16 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2003-04-02 18:43:16 +0000 |
| commit | af22f5b24a0ca6ff93ca536bf12a6b6afb3713a2 (patch) | |
| tree | 87e20f0c67778f5b3e5f17d601f56b57c5080293 /gas/testsuite/gas/mips/ulw2-eb.d | |
| parent | 8fdeb6e3c534eef6c31a5152448d9e1fa995ddc4 (diff) | |
| download | ppe42-binutils-af22f5b24a0ca6ff93ca536bf12a6b6afb3713a2.tar.gz ppe42-binutils-af22f5b24a0ca6ff93ca536bf12a6b6afb3713a2.zip | |
[ gas/ChangeLog ]
2003-04-02 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro2): Adjust implementation of
M_ULH, M_ULHU, M_ULW, and M_ULD so that they work properly
in the case where the source and destination registers
are the same.
[ gas/testsuite/ChangeLog ]
2003-04-02 Chris Demetriou <cgd@broadcom.com>
* gas/mips/ulh.d: Adjust for ulh and ulhu macro assembly changes.
* gas/mips/mips.exp: Define new "gpr_ilocks" architecture
property, and add it to mips2 (and later) chips and r3900.
* gas/mips/uld2.s: New test source file.
* gas/mips/ulh2.s: Likewise.
* gas/mips/ulw2.s: Likewise.
* gas/mips/uld2.l: New test stderr listing.
* gas/mips/ulh2.l: Likewise.
* gas/mips/ulw2.l: Likewise.
* gas/mips/uld2-eb.d: New test.
* gas/mips/uld2-el.d: Likewise.
* gas/mips/ulh2-eb.d: Likewise.
* gas/mips/ulh2-el.d: Likewise.
* gas/mips/ulw2-eb-ilocks.d: Likewise.
* gas/mips/ulw2-eb.d: Likewise.
* gas/mips/ulw2-el-ilocks.d: Likewise.
* gas/mips/ulw2-el.d: Likewise.
* gas/mips/mips.exp: Run new tests for appropriate architectures.
Diffstat (limited to 'gas/testsuite/gas/mips/ulw2-eb.d')
| -rw-r--r-- | gas/testsuite/gas/mips/ulw2-eb.d | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/gas/testsuite/gas/mips/ulw2-eb.d b/gas/testsuite/gas/mips/ulw2-eb.d new file mode 100644 index 0000000000..cb7cae6e7b --- /dev/null +++ b/gas/testsuite/gas/mips/ulw2-eb.d @@ -0,0 +1,28 @@ +#as: -EB +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: ulw2 -EB non-interlocked +#source: ulw2.s +#stderr: ulw2.l + +# Further checks of ulw macro. +# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the +# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu) +# XXX: should be changed to be 'or' instructions and this comment should be +# XXX: removed. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 88a40000 lwl \$4,0\(\$5\) +0+0004 <[^>]*> 98a40003 lwr \$4,3\(\$5\) +0+0008 <[^>]*> 88a40001 lwl \$4,1\(\$5\) +0+000c <[^>]*> 98a40004 lwr \$4,4\(\$5\) +0+0010 <[^>]*> 88a10000 lwl \$1,0\(\$5\) +0+0014 <[^>]*> 98a10003 lwr \$1,3\(\$5\) +0+0018 <[^>]*> 00000000 nop +0+001c <[^>]*> 0020282[1d] move \$5,\$1 +0+0020 <[^>]*> 88a10001 lwl \$1,1\(\$5\) +0+0024 <[^>]*> 98a10004 lwr \$1,4\(\$5\) +0+0028 <[^>]*> 00000000 nop +0+002c <[^>]*> 0020282[1d] move \$5,\$1 + \.\.\. |
