diff options
| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-14 13:07:50 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-14 13:07:50 +0000 |
| commit | 7a5f87ce9bd0d5facacd10424c26deb0af041630 (patch) | |
| tree | d44ee0ef601816444ded5e695238a4bc96dd8a2d | |
| parent | 5b581c314777475df0cc607c33861e87c5c3de77 (diff) | |
| download | ppe42-binutils-7a5f87ce9bd0d5facacd10424c26deb0af041630.tar.gz ppe42-binutils-7a5f87ce9bd0d5facacd10424c26deb0af041630.zip | |
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
ADDA.S, MULA.S and SUBA.S.
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 905b37e1e3..6478052a59 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> + + * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for + ADDA.S, MULA.S and SUBA.S. + 2013-07-08 H.J. Lu <hongjiu.lu@intel.com> PR gas/13572 diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 9a80de6428..e6833f7438 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -314,7 +314,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX }, {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX }, {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX }, -{"adda.s", "V,T", 0x46000018, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, +{"adda.s", "S,T", 0x46000018, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX }, @@ -1157,7 +1157,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX }, {"mula.ob", "S,Q", 0x48000033, 0xfc2007ff, WR_CC|RD_S|RD_T, 0, N54 }, {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX }, -{"mula.s", "V,T", 0x4600001a, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, +{"mula.s", "S,T", 0x4600001a, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX }, @@ -1528,7 +1528,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX }, {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX }, {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX }, -{"suba.s", "V,T", 0x46000019, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, +{"suba.s", "S,T", 0x46000019, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, {"subu", "D,S,T", 0x45800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, |
