diff options
| author | Xo Wang <xow@google.com> | 2017-01-03 14:51:09 -0800 |
|---|---|---|
| committer | Xo Wang <xow@google.com> | 2017-01-10 17:40:39 -0800 |
| commit | 20dccacccffc26ab83389d4cad9da7414c2ecb0b (patch) | |
| tree | f072ee0ba5a65d01bc3cd51613d338319d3633f0 /libpdbg/bmcfsi.c | |
| parent | e4d626ed4edc3db0b850e71ca0410e343faca950 (diff) | |
| download | pdbg-20dccacccffc26ab83389d4cad9da7414c2ecb0b.tar.gz pdbg-20dccacccffc26ab83389d4cad9da7414c2ecb0b.zip | |
libpdbg/bmcfsi: Update Zaius pin assignments for EVT2
Update pin assignments for the board revision that replaces all current
Zaius boards.
The schematic indicates pins G0 and G1 for clock and data but contains
an error that forced rework for all EVT2 and EVT3 boards to use C3 and
C2 for FSI.
Signed-off-by: Xo Wang <xow@google.com>
Diffstat (limited to 'libpdbg/bmcfsi.c')
| -rw-r--r-- | libpdbg/bmcfsi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/libpdbg/bmcfsi.c b/libpdbg/bmcfsi.c index fcd160d..61f719f 100644 --- a/libpdbg/bmcfsi.c +++ b/libpdbg/bmcfsi.c @@ -83,8 +83,8 @@ struct gpio_pin p9r_gpio_pins[] = { #define P9R_CLOCK_DELAY 20 struct gpio_pin p9z_gpio_pins[] = { - {0x1e0, 16}, /* FSI_CLK = AA0 */ - {0x20, 0}, /* FSI_DAT = E0 */ + {0, 19}, /* FSI_CLK = C3 */ + {0, 18}, /* FSI_DAT = C2 */ {0x78, 22}, /* FSI_DAT_EN = O6 */ {0, 24}, /* FSI_ENABLE = D0 */ {0x78, 30}, /* CRONUS_SEL = P6 */ |
