libpdbg/p8chip.c: ram state setup sequence match workbook

This makes a few changes to stop and ram procedure.

First of all, the existing thread_stop procedure is also setting up some
of the ram state. Change that to just do the stop sequence from the
workbook, and move the ram stuff into ram setup and destroy.

The workbook calls for inactive threads being rammed to set a thread
active state before ram mode is exited, in order for GPRs modified by
ramming to avoid getting lost. Currently the code does that in the
stop sequence before ram mode is activated.

The code also currently deasserts the thread active bit after exiting
ram mode, which is not part of the workbook, so this is no longer done.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

1 files changed, 13 insertions, 28 deletions

diff --git a/libpdbg/p8chip.c b/libpdbg/p8chip.c
index b9fa26d..a12c2fe 100644
--- a/libpdbg/p8chip.c
+++ b/libpdbg/p8chip.c
@@ -278,8 +278,6 @@ static int p8_thread_stop(struct thread *thread)
 {
 	int i = 0;
 	uint64_t val;
-	struct core *chip = target_to_core(
-		pdbg_target_require_parent("core", &thread->target));
 
 	/* Quiese active thread */
 	CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_STOP));
@@ -298,39 +296,17 @@ static int p8_thread_stop(struct thread *thread)
 			}
 			break;
 		}
-
-		/* We can continue ramming if either the
-		 * thread is not active or the SRQ/LSU/TS bits
-		 * are set. */
-	} while ((val & RAS_STATUS_THREAD_ACTIVE) &&
-		 !((val & RAS_STATUS_SRQ_EMPTY)
-		   && (val & RAS_STATUS_LSU_QUIESCED)
-		   && (val & RAS_STATUS_TS_QUIESCE)));
-
-
-	/* Make the threads RAM thread active */
-	CHECK_ERR(pib_read(&chip->target, THREAD_ACTIVE_REG, &val));
-	val |= PPC_BIT(8) >> thread->id;
-	CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val));
+	} while (!(val & RAS_STATUS_INST_COMPLETE) &&
+		 !(val & RAS_STATUS_TS_QUIESCE));
 
 	return 0;
 }
 
 static int p8_thread_start(struct thread *thread)
 {
-	uint64_t val;
-	struct core *chip = target_to_core(
-		pdbg_target_require_parent("core", &thread->target));
-
 	/* Activate thread */
 	CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_START));
 
-	/* Restore thread active */
-	CHECK_ERR(pib_read(&chip->target, THREAD_ACTIVE_REG, &val));
-	val &= ~(PPC_BIT(8) >> thread->id);
-	val |= PPC_BIT(thread->id);
-	CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val));
-
 	return 0;
 }
 
@@ -365,8 +341,10 @@ static int p8_ram_setup(struct thread *thread)
 			return 1;
 	}
 
-	if (!(thread->status.active))
+	if (!(thread->status.active)) {
+		PR_WARNING("Thread is in power save state, can not RAM\n");
 		return 2;
+	}
 
 	/* Activate RAM mode */
 	CHECK_ERR(pib_read(&chip->target, RAM_MODE_REG, &ram_mode));
@@ -425,7 +403,14 @@ static int p8_ram_destroy(struct thread *thread)
 {
 	struct core *chip = target_to_core(
 		pdbg_target_require_parent("core", &thread->target));
-	uint64_t ram_mode;
+	uint64_t val, ram_mode;
+
+	if (!(get_thread_status(thread).active)) {
+		/* Mark the RAM thread active so GPRs stick */
+		CHECK_ERR(pib_read(&chip->target, THREAD_ACTIVE_REG, &val));
+		val |= PPC_BIT(8) >> thread->id;
+		CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val));
+	}
 
 	/* Disable RAM mode */
 	CHECK_ERR(pib_read(&chip->target, RAM_MODE_REG, &ram_mode));