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authorNicholas Piggin <npiggin@gmail.com>2019-03-12 11:49:19 +1000
committerAlistair Popple <alistair@popple.id.au>2019-03-27 16:57:16 +1100
commitdccba372193c95469de633144c1f3ba2ba8ac223 (patch)
tree3fc8ebd76a269105af4fc620c662976a69615b85
parent5a5334451cd22a40bc21b41789fcd74e04eb28ba (diff)
downloadpdbg-dccba372193c95469de633144c1f3ba2ba8ac223.zip
pdbg-dccba372193c95469de633144c1f3ba2ba8ac223.tar.gz
libpdbg/p8chip.c: ram state setup sequence match workbook
This makes a few changes to stop and ram procedure. First of all, the existing thread_stop procedure is also setting up some of the ram state. Change that to just do the stop sequence from the workbook, and move the ram stuff into ram setup and destroy. The workbook calls for inactive threads being rammed to set a thread active state before ram mode is exited, in order for GPRs modified by ramming to avoid getting lost. Currently the code does that in the stop sequence before ram mode is activated. The code also currently deasserts the thread active bit after exiting ram mode, which is not part of the workbook, so this is no longer done. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
-rw-r--r--libpdbg/p8chip.c41
1 files changed, 13 insertions, 28 deletions
diff --git a/libpdbg/p8chip.c b/libpdbg/p8chip.c
index 71e6569..cd4a50b 100644
--- a/libpdbg/p8chip.c
+++ b/libpdbg/p8chip.c
@@ -278,8 +278,6 @@ static int p8_thread_stop(struct thread *thread)
{
int i = 0;
uint64_t val;
- struct core *chip = target_to_core(
- pdbg_target_require_parent("core", &thread->target));
/* Quiese active thread */
CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_STOP));
@@ -298,20 +296,8 @@ static int p8_thread_stop(struct thread *thread)
}
break;
}
-
- /* We can continue ramming if either the
- * thread is not active or the SRQ/LSU/TS bits
- * are set. */
- } while ((val & RAS_STATUS_THREAD_ACTIVE) &&
- !((val & RAS_STATUS_SRQ_EMPTY)
- && (val & RAS_STATUS_LSU_QUIESCED)
- && (val & RAS_STATUS_TS_QUIESCE)));
-
-
- /* Make the threads RAM thread active */
- CHECK_ERR(pib_read(&chip->target, THREAD_ACTIVE_REG, &val));
- val |= PPC_BIT(8) >> thread->id;
- CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val));
+ } while (!(val & RAS_STATUS_INST_COMPLETE) &&
+ !(val & RAS_STATUS_TS_QUIESCE));
thread->status = get_thread_status(thread);
@@ -320,19 +306,9 @@ static int p8_thread_stop(struct thread *thread)
static int p8_thread_start(struct thread *thread)
{
- uint64_t val;
- struct core *chip = target_to_core(
- pdbg_target_require_parent("core", &thread->target));
-
/* Activate thread */
CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_START));
- /* Restore thread active */
- CHECK_ERR(pib_read(&chip->target, THREAD_ACTIVE_REG, &val));
- val &= ~(PPC_BIT(8) >> thread->id);
- val |= PPC_BIT(thread->id);
- CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val));
-
thread->status = get_thread_status(thread);
return 0;
@@ -369,8 +345,10 @@ static int p8_ram_setup(struct thread *thread)
return 1;
}
- if (!(thread->status.active))
+ if (!(thread->status.active)) {
+ PR_WARNING("Thread is in power save state, can not RAM\n");
return 2;
+ }
/* Activate RAM mode */
CHECK_ERR(pib_read(&chip->target, RAM_MODE_REG, &ram_mode));
@@ -429,7 +407,14 @@ static int p8_ram_destroy(struct thread *thread)
{
struct core *chip = target_to_core(
pdbg_target_require_parent("core", &thread->target));
- uint64_t ram_mode;
+ uint64_t val, ram_mode;
+
+ if (!(get_thread_status(thread).active)) {
+ /* Mark the RAM thread active so GPRs stick */
+ CHECK_ERR(pib_read(&chip->target, THREAD_ACTIVE_REG, &val));
+ val |= PPC_BIT(8) >> thread->id;
+ CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val));
+ }
/* Disable RAM mode */
CHECK_ERR(pib_read(&chip->target, RAM_MODE_REG, &ram_mode));
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