| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The bus that is read may only show up at certain
times, such as during poweron. It is not
a fatal error condition if the bus is not available.
So we will let it get logged to the journal, but not
let it get committed in this case.
Tested: It was an intermittent failure, but ran
poweron/poweroff a few times and didn't see
the error pop up again.
Resolves: openbmc/openbmc#3510
Change-Id: I47629e5f27fb847aa0094f0757b1988f8e645ebc
Signed-off-by: Anthony Wilson <wilsonan@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
This code always just runs in the power off path, and at times it
may be called when power is already off. In that case the FSI
access would fail since the processor won't have power, so just
catch the error and continue on.
Change-Id: Ic02b17875763b0540edaaec47ee19846f305db72
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
This was keeping hostboot from using some default scratch
register settings.
Tested: Tested by HW team
Change-Id: I1290acbabfa785e67a6038a3aadb7ececd9e1f7a
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
|
|
|
|
|
|
|
|
| |
Procedure should be run on all of the master and
slave CPUs.
Change-Id: I323519b059cfbe14ccd6145e22b1bdae4fd3d476
Signed-off-by: Anthony Wilson <wilsonan@us.ibm.com>
|
|
|
|
|
| |
Change-Id: Ia8c516ca1a4ceca46a88c9de72cd765e3b2884c2
Signed-off-by: Anthony Wilson <wilsonan@us.ibm.com>
|
|
|
|
|
|
|
| |
Add .clang-format for automatic style.
Change-Id: I6d240009370179b5b8f1f646b0476a059ec6aa85
Signed-off-by: Patrick Venture <venture@google.com>
|
|
|
|
|
|
|
| |
Compiler complaining about the copyright characters.
Change-Id: I6730a50a668899a33e9dfcc4accb67ee207a3f08
Signed-off-by: Patrick Venture <venture@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This disables the drivers and receiver in the
PCIE root control 1 register as follows:
BIT NAME VALUE
19 TP_RI_DC_B 0b0
20 TP_DI1_DC_B 0b0
21 TP_DI2_DC_B 0b0
This should be run on a power off.
Change-Id: I6e027260f78a3fc451a45832f6f9bcf9afc8c3b9
Signed-off-by: Anthony Wilson <wilsonan@us.ibm.com>
|
|
|
|
|
|
|
|
| |
1. SBE istep info (cfam 2809)
2. HB istep info (cfam 283C)
Change-Id: I67632c58fe1148b980791dc017e5c099107caae5
Signed-off-by: Shakeeb Pasha <shakeebbk@in.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This procedure will perform both the FSI master
and FSI hub scans.
It replaces doing the scans by writing to sysfs
using the echo command so that real errors can
be created on failures.
Currently the only way to tell if the master scan
fails is by checking for missing sysfs files, and
this code will do that by checking for the hub
scan file.
Change-Id: Id4b91592b8c8b9a5fc9f1a56f4d89e142a6c6b74
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
Remove the local error definitions and use the
ones in phosphor-dbus-interfaces instead as the ones
there suit our purposes and it simplifies this repository
to do so.
Change-Id: I18428c496914153270ecb181e7193acd0e386e97
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Recent code changes now decrement the boot count at
the start of every boot. The sbe side select design
is to boot from side 0 twice, then side 1 on the
last attempt. Now that the boot count is decremented
at the start of the boot (and the total boot count is 3),
the software needs to use side 0 when the boot count
is greater than or equal to 1.
Resolves openbmc/openbmc#2169
Change-Id: Ic08bed34d58de3d40b742ce52ca83627976d8fee
Signed-off-by: Andrew Geissler <andrewg@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The VCS workaround is only required (and only make sense)
on P9 DD1.0 based systems. This code does a check of the
chip level and does not run the workaround if the chip
is not DD1.0.
The code will continue to run some of the other workarounds
because although not required for non-dd10 chips, they
do no harm.
Resolves openbmc/openbmc#1695
Change-Id: I1409ca359ccff7b78a186211e4cd447cd753eda7
Signed-off-by: Andrew Geissler <andrewg@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The default side for the SBE to boot from is side 0, which
is indicated by a 0 in bit 17 of cfam 0x2808.
When the boot count goes to 1 (the last before giving up), the
start_host logic will switch over to side 1 for the SBE to
boot from.
Resolves openbmc/openbmc#1467
Change-Id: I61aa22939baa4cde38c8716429b6ca55f7c850bd
Signed-off-by: Andrew Geissler <andrewg@us.ibm.com>
|
|
|
|
|
|
|
| |
Resolves openbmc/openbmc#1323
Change-Id: Ia93d1f0036341c26fdc6c5e3133d4a05346090be
Signed-off-by: Dhruvaraj Subhashchandran <dhruvaraj@in.ibm.com>
|
|
|
|
|
|
|
|
|
| |
This new procedure will allow users to
provide P9 CFAM register overrides
before the P9 SBE is started.
Change-Id: If3658f9a6ede9a3682c4ed7888e9acb328c67709
Signed-off-by: Michael Tritz <mtritz@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
This procedure is required when switching to external
cronus mode which needs synchronous FSI clock mode set
as opposed to the asynchronous mode required by the Open FSI
driver.
Change-Id: I509d113bd5cdadedb64b0275628f95572c21b0a3
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
For a procedure to be available to run, it needs to have
a call to a REGISTER_PROCEDURE macro. This macro wraps
a call to a Register class that adds the procedure to the list
along with the name to call it.
Change-Id: I20d02e8f004c1c726228469465ae89b60ee52d66
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
|
|
Procedures will now be in procedures/<chip>/.
The next commit will have the procedures register
themselves so they won't be in a hardcoded list.
Change-Id: I0ff90afe2b51aaff25b5c25bf87070c820323e30
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
|