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authorAndrew Geissler <andrewg@us.ibm.com>2017-06-08 15:36:09 -0500
committerAndrew Geissler <andrewg@us.ibm.com>2017-06-09 08:28:06 -0500
commit16e099a76314a8de8e89c31a87232226551bd09d (patch)
treecfb922ce72c4a96ebb6f605214a5098e6f26be55 /p9_cfam.hpp
parent2548c7a35ab2ac8d8d73b8b8f5145d64f248ebe1 (diff)
downloadopenpower-proc-control-16e099a76314a8de8e89c31a87232226551bd09d.tar.gz
openpower-proc-control-16e099a76314a8de8e89c31a87232226551bd09d.zip
Don't run vcs workaround on non-dd10 chips
The VCS workaround is only required (and only make sense) on P9 DD1.0 based systems. This code does a check of the chip level and does not run the workaround if the chip is not DD1.0. The code will continue to run some of the other workarounds because although not required for non-dd10 chips, they do no harm. Resolves openbmc/openbmc#1695 Change-Id: I1409ca359ccff7b78a186211e4cd447cd753eda7 Signed-off-by: Andrew Geissler <andrewg@us.ibm.com>
Diffstat (limited to 'p9_cfam.hpp')
-rw-r--r--p9_cfam.hpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/p9_cfam.hpp b/p9_cfam.hpp
index 07b251d..0cf5c02 100644
--- a/p9_cfam.hpp
+++ b/p9_cfam.hpp
@@ -6,8 +6,12 @@ namespace cfam
{
namespace p9
{
+
+static constexpr uint32_t P9_DD10_CHIPID = 0x120D1049;
+
static constexpr uint16_t P9_FSI_A_SI1S = 0x081C;
static constexpr uint16_t P9_LL_MODE_REG = 0x0840;
+static constexpr uint16_t P9_FSI2PIB_CHIPID = 0x100A;
static constexpr uint16_t P9_FSI2PIB_INTERRUPT = 0x100B;
static constexpr uint16_t P9_FSI2PIB_TRUE_MASK = 0x100D;
static constexpr uint16_t P9_CBS_CS = 0x2801;
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