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authorMatt Spinler <spinler@us.ibm.com>2017-03-28 16:01:52 -0500
committerMatt Spinler <spinler@us.ibm.com>2017-03-30 08:55:58 -0500
commit4bf58971b7ee8d25855b4339b64d2708f1626c41 (patch)
tree4f6c13bd5fe023527f2be28054e33fcf72ff233c
parentb65423413a236431a5ac53123bf568427610c190 (diff)
downloadopenpower-proc-control-4bf58971b7ee8d25855b4339b64d2708f1626c41.tar.gz
openpower-proc-control-4bf58971b7ee8d25855b4339b64d2708f1626c41.zip
New procedure to set synchronous FSI clock mode
This procedure is required when switching to external cronus mode which needs synchronous FSI clock mode set as opposed to the asynchronous mode required by the Open FSI driver. Change-Id: I509d113bd5cdadedb64b0275628f95572c21b0a3 Signed-off-by: Matt Spinler <spinler@us.ibm.com>
-rw-r--r--procedures/p9/set_sync_fsi_clock_mode.cpp48
1 files changed, 48 insertions, 0 deletions
diff --git a/procedures/p9/set_sync_fsi_clock_mode.cpp b/procedures/p9/set_sync_fsi_clock_mode.cpp
new file mode 100644
index 0000000..1751a9d
--- /dev/null
+++ b/procedures/p9/set_sync_fsi_clock_mode.cpp
@@ -0,0 +1,48 @@
+/**
+ * Copyright © 2017 IBM Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cfam_access.hpp"
+#include "p9_cfam.hpp"
+#include "registration.hpp"
+#include "targeting.hpp"
+
+namespace openpower
+{
+namespace p9
+{
+
+using namespace openpower::cfam::access;
+using namespace openpower::cfam::p9;
+using namespace openpower::targeting;
+
+
+/**
+ * @Brief Sets the P9 FSI clock to synchronous mode.
+ */
+void setSynchronousFSIClock()
+{
+ Targeting targets;
+ const auto& master = *(targets.begin());
+
+ //Set bit 31 to 0
+ writeRegWithMask(master, P9_LL_MODE_REG, 0x00000000, 0x00000001);
+}
+
+
+REGISTER_PROCEDURE("setSyncFSIClock", setSynchronousFSIClock);
+
+}
+}
+
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