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authorVicente Olivert Riera <Vincent.Riera@imgtec.com>2016-09-30 10:36:49 +0100
committerPeter Korsgaard <peter@korsgaard.com>2016-10-15 13:22:17 +0200
commit45c92c60b163abefb0e78fe4f992d7cbbdaa72e8 (patch)
tree4d3d1b1a8c94f23d0a3626e3ed14f8526ed130e0 /package/openblas
parentf62cbd75b7f56d1842c9d59e6779b0e869d164f9 (diff)
downloadbuildroot-45c92c60b163abefb0e78fe4f992d7cbbdaa72e8.tar.gz
buildroot-45c92c60b163abefb0e78fe4f992d7cbbdaa72e8.zip
MIPS: replace every BR2_mips_* with the new MIPS CPU options
Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Diffstat (limited to 'package/openblas')
-rw-r--r--package/openblas/Config.in6
1 files changed, 3 insertions, 3 deletions
diff --git a/package/openblas/Config.in b/package/openblas/Config.in
index 0609a91e54..1fbed1c27a 100644
--- a/package/openblas/Config.in
+++ b/package/openblas/Config.in
@@ -27,10 +27,10 @@ config BR2_PACKAGE_OPENBLAS_DEFAULT_TARGET
default "PPC440" if BR2_powerpc_440
default "PPC440FP2" if BR2_powerpc_440fp
# P5600 is built with MSA support which is only available in Codescape toolchains
- default "P5600" if BR2_mips_32r2 && BR2_TOOLCHAIN_EXTERNAL_CODESCAPE_MTI_MIPS
- default "SICORTEX" if BR2_mips_64
+ default "P5600" if BR2_MIPS_CPU_MIPS32R2 && BR2_TOOLCHAIN_EXTERNAL_CODESCAPE_MTI_MIPS
+ default "SICORTEX" if BR2_MIPS_CPU_MIPS64
# I6400 is built with MSA support which is only available in Codescape toolchains
- default "I6400" if BR2_mips_64r6 && BR2_TOOLCHAIN_EXTERNAL_CODESCAPE_IMG_MIPS
+ default "I6400" if BR2_MIPS_CPU_MIPS64R6 && BR2_TOOLCHAIN_EXTERNAL_CODESCAPE_IMG_MIPS
default "SPARC" if BR2_sparc
# Cortex-A15 always have a VFPv4
default "CORTEXA15" if (BR2_cortex_a15 && BR2_ARM_EABIHF)
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