gcc: bump 4.9.x series to version 4.9.2

Drop PR60102 patch which is now upstream.

Signed-off-by: Gustavo Zacarias <gustavo@zacarias.com.ar>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

10 files changed, 1 insertions, 389 deletions

diff --git a/package/gcc/4.9.1/841-PR60102.patch b/package/gcc/4.9.1/841-PR60102.patch
deleted file mode 100644
index e34695de58..0000000000
--- a/package/gcc/4.9.1/841-PR60102.patch
+++ /dev/null
@@ -1,388 +0,0 @@
-From https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60102
-Target: 4.9.2
-
-Signed-off-by: Gustavo Zacarias <gustavo@zacarias.com.ar>
-
-diff -Nura gcc-4.9.1.orig/gcc/config/rs6000/rs6000.c gcc-4.9.1/gcc/config/rs6000/rs6000.c
---- gcc-4.9.1.orig/gcc/config/rs6000/rs6000.c	2014-08-05 14:53:37.294498582 -0300
-+++ gcc-4.9.1/gcc/config/rs6000/rs6000.c	2014-08-05 14:58:33.972555735 -0300
-@@ -1221,7 +1221,12 @@
-       /* Soft frame pointer.  */
-       "sfp",
-       /* HTM SPR registers.  */
--      "tfhar", "tfiar", "texasr"
-+      "tfhar", "tfiar", "texasr",
-+      /* SPE High registers.  */
-+      "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
-+      "8",  "9", "10", "11", "12", "13", "14", "15",
-+     "16", "17", "18", "19", "20", "21", "22", "23",
-+     "24", "25", "26", "27", "28", "29", "30", "31"
- };
- 
- #ifdef TARGET_REGNAMES
-@@ -1249,7 +1254,12 @@
-   /* Soft frame pointer.  */
-   "sfp",
-   /* HTM SPR registers.  */
--  "tfhar", "tfiar", "texasr"
-+  "tfhar", "tfiar", "texasr",
-+  /* SPE High registers.  */
-+  "%rh0",  "%rh1",  "%rh2",  "%rh3",  "%rh4",  "%rh5",  "%rh6",   "%rh7",
-+  "%rh8",  "%rh9",  "%rh10", "%r11",  "%rh12", "%rh13", "%rh14", "%rh15",
-+  "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
-+  "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
- };
- #endif
- 
-@@ -31074,13 +31084,13 @@
-     {
-       if (BYTES_BIG_ENDIAN)
- 	{
--	  parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
-+	  parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
- 	  parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
- 	}
-       else
- 	{
- 	  parts[2 * i] = gen_rtx_REG (SImode, regno);
--	  parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
-+	  parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
- 	}
-     }
- 
-@@ -31100,11 +31110,11 @@
-       rtx mem = gen_rtx_MEM (BLKmode, addr);
-       rtx value = gen_int_mode (4, mode);
- 
--      for (i = 1201; i < 1232; i++)
-+      for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++)
- 	{
--	  int column = DWARF_REG_TO_UNWIND_COLUMN (i);
--	  HOST_WIDE_INT offset
--	    = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
-+	  int column = DWARF_REG_TO_UNWIND_COLUMN
-+		(DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
-+	  HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
- 
- 	  emit_move_insn (adjust_address (mem, mode, offset), value);
- 	}
-@@ -31123,9 +31133,9 @@
- 
-       for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
- 	{
--	  int column = DWARF_REG_TO_UNWIND_COLUMN (i);
--	  HOST_WIDE_INT offset
--	    = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
-+	  int column = DWARF_REG_TO_UNWIND_COLUMN
-+		(DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
-+	  HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
- 
- 	  emit_move_insn (adjust_address (mem, mode, offset), value);
- 	}
-@@ -31157,9 +31167,8 @@
-     return 99;
-   if (regno == SPEFSCR_REGNO)
-     return 612;
--  /* SPE high reg number.  We get these values of regno from
--     rs6000_dwarf_register_span.  */
--  gcc_assert (regno >= 1200 && regno < 1232);
-+  if (SPE_HIGH_REGNO_P (regno))
-+    return regno - FIRST_SPE_HIGH_REGNO + 1200;
-   return regno;
- }
- 
-diff -Nura gcc-4.9.1.orig/gcc/config/rs6000/rs6000.h gcc-4.9.1/gcc/config/rs6000/rs6000.h
---- gcc-4.9.1.orig/gcc/config/rs6000/rs6000.h	2014-08-05 14:53:37.291498480 -0300
-+++ gcc-4.9.1/gcc/config/rs6000/rs6000.h	2014-08-05 14:58:33.974555802 -0300
-@@ -930,35 +930,36 @@
- 
-    The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS.  */
- 
--#define FIRST_PSEUDO_REGISTER 117
-+#define FIRST_PSEUDO_REGISTER 149
- 
- /* This must be included for pre gcc 3.0 glibc compatibility.  */
- #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
- 
--/* Add 32 dwarf columns for synthetic SPE registers.  */
--#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32)
-+/* True if register is an SPE High register.  */
-+#define SPE_HIGH_REGNO_P(N) \
-+  ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
-+
-+/* SPE high registers added as hard regs.
-+   The sfp register and 3 HTM registers
-+   aren't included in DWARF_FRAME_REGISTERS.  */
-+#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
- 
- /* The SPE has an additional 32 synthetic registers, with DWARF debug
-    info numbering for these registers starting at 1200.  While eh_frame
-    register numbering need not be the same as the debug info numbering,
--   we choose to number these regs for eh_frame at 1200 too.  This allows
--   future versions of the rs6000 backend to add hard registers and
--   continue to use the gcc hard register numbering for eh_frame.  If the
--   extra SPE registers in eh_frame were numbered starting from the
--   current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
--   changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
--   avoid invalidating older SPE eh_frame info.
-+   we choose to number these regs for eh_frame at 1200 too.
- 
-    We must map them here to avoid huge unwinder tables mostly consisting
-    of unused space.  */
- #define DWARF_REG_TO_UNWIND_COLUMN(r) \
--  ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
-+  ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
- 
- /* Use standard DWARF numbering for DWARF debugging information.  */
- #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
- 
- /* Use gcc hard register numbering for eh_frame.  */
--#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
-+#define DWARF_FRAME_REGNUM(REGNO) \
-+  (SPE_HIGH_REGNO_P (REGNO) ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO))
- 
- /* Map register numbers held in the call frame info that gcc has
-    collected using DWARF_FRAME_REGNUM to those that should be output in
-@@ -992,7 +993,10 @@
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-    1, 1						   \
--   , 1, 1, 1, 1, 1, 1				   \
-+   , 1, 1, 1, 1, 1, 1,				   \
-+   /* SPE High registers.  */			   \
-+   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-+   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1  \
- }
- 
- /* 1 for registers not available across function calls.
-@@ -1012,7 +1016,10 @@
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-    1, 1						   \
--   , 1, 1, 1, 1, 1, 1				   \
-+   , 1, 1, 1, 1, 1, 1,				   \
-+   /* SPE High registers.  */			   \
-+   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-+   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1  \
- }
- 
- /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
-@@ -1031,7 +1038,10 @@
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-    0, 0						   \
--   , 0, 0, 0, 0, 0, 0				   \
-+   , 0, 0, 0, 0, 0, 0,				   \
-+   /* SPE High registers.  */			   \
-+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-+   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0  \
- }
- 
- #define TOTAL_ALTIVEC_REGS	(LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
-@@ -1114,7 +1124,10 @@
-    96, 95, 94, 93, 92, 91,					\
-    108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97,	\
-    109, 110,							\
--   111, 112, 113, 114, 115, 116					\
-+   111, 112, 113, 114, 115, 116,				\
-+   117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128,  \
-+   129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140,  \
-+   141, 142, 143, 144, 145, 146, 147, 148			\
- }
- 
- /* True if register is floating-point.  */
-@@ -1349,6 +1362,7 @@
-   CR_REGS,
-   NON_FLOAT_REGS,
-   CA_REGS,
-+  SPE_HIGH_REGS,
-   ALL_REGS,
-   LIM_REG_CLASSES
- };
-@@ -1380,6 +1394,7 @@
-   "CR_REGS",								\
-   "NON_FLOAT_REGS",							\
-   "CA_REGS",								\
-+  "SPE_HIGH_REGS",							\
-   "ALL_REGS"								\
- }
- 
-@@ -1387,30 +1402,54 @@
-    This is an initializer for a vector of HARD_REG_SET
-    of length N_REG_CLASSES.  */
- 
--#define REG_CLASS_CONTENTS						     \
--{									     \
--  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */	     \
--  { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */	     \
--  { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */     \
--  { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */       \
--  { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */     \
--  { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */	     \
--  { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */	     \
--  { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */	     \
--  { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */     \
--  { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */     \
--  { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */     \
--  { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
--  { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */	     \
--  { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */	     \
--  { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
--  { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */     \
--  { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
--  { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */	     \
--  { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */	     \
--  { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */   \
--  { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */	     \
--  { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff }  /* ALL_REGS */	     \
-+#define REG_CLASS_CONTENTS						\
-+{									\
-+  /* NO_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	\
-+  /* BASE_REGS.  */							\
-+  { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 },	\
-+  /* GENERAL_REGS.  */							\
-+  { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 },	\
-+  /* FLOAT_REGS.  */							\
-+  { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 },	\
-+  /* ALTIVEC_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 },	\
-+  /* VSX_REGS.  */							\
-+  { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 },	\
-+  /* VRSAVE_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 },	\
-+  /* VSCR_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 },	\
-+  /* SPE_ACC_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 },	\
-+  /* SPEFSCR_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 },	\
-+  /* SPR_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 },	\
-+  /* NON_SPECIAL_REGS.  */						\
-+  { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 },	\
-+  /* LINK_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 },	\
-+  /* CTR_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 },	\
-+  /* LINK_OR_CTR_REGS.  */						\
-+  { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 },	\
-+  /* SPECIAL_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 },	\
-+  /* SPEC_OR_GEN_REGS.  */						\
-+  { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 },	\
-+  /* CR0_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 },	\
-+  /* CR_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 },	\
-+  /* NON_FLOAT_REGS.  */						\
-+  { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 },	\
-+  /* CA_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 },	\
-+  /* SPE_HIGH_REGS.  */							\
-+  { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff },	\
-+  /* ALL_REGS.  */							\
-+  { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff }	\
- }
- 
- /* The same information, inverted:
-@@ -2349,6 +2388,39 @@
-   &rs6000_reg_names[114][0],	/* tfhar  */				\
-   &rs6000_reg_names[115][0],	/* tfiar  */				\
-   &rs6000_reg_names[116][0],	/* texasr  */				\
-+									\
-+  &rs6000_reg_names[117][0],	/* SPE rh0.  */				\
-+  &rs6000_reg_names[118][0],	/* SPE rh1.  */				\
-+  &rs6000_reg_names[119][0],	/* SPE rh2.  */				\
-+  &rs6000_reg_names[120][0],	/* SPE rh3.  */				\
-+  &rs6000_reg_names[121][0],	/* SPE rh4.  */				\
-+  &rs6000_reg_names[122][0],	/* SPE rh5.  */				\
-+  &rs6000_reg_names[123][0],	/* SPE rh6.  */				\
-+  &rs6000_reg_names[124][0],	/* SPE rh7.  */				\
-+  &rs6000_reg_names[125][0],	/* SPE rh8.  */				\
-+  &rs6000_reg_names[126][0],	/* SPE rh9.  */				\
-+  &rs6000_reg_names[127][0],	/* SPE rh10.  */			\
-+  &rs6000_reg_names[128][0],	/* SPE rh11.  */			\
-+  &rs6000_reg_names[129][0],	/* SPE rh12.  */			\
-+  &rs6000_reg_names[130][0],	/* SPE rh13.  */			\
-+  &rs6000_reg_names[131][0],	/* SPE rh14.  */			\
-+  &rs6000_reg_names[132][0],	/* SPE rh15.  */			\
-+  &rs6000_reg_names[133][0],	/* SPE rh16.  */			\
-+  &rs6000_reg_names[134][0],	/* SPE rh17.  */			\
-+  &rs6000_reg_names[135][0],	/* SPE rh18.  */			\
-+  &rs6000_reg_names[136][0],	/* SPE rh19.  */			\
-+  &rs6000_reg_names[137][0],	/* SPE rh20.  */			\
-+  &rs6000_reg_names[138][0],	/* SPE rh21.  */			\
-+  &rs6000_reg_names[139][0],	/* SPE rh22.  */			\
-+  &rs6000_reg_names[140][0],	/* SPE rh22.  */			\
-+  &rs6000_reg_names[141][0],	/* SPE rh24.  */			\
-+  &rs6000_reg_names[142][0],	/* SPE rh25.  */			\
-+  &rs6000_reg_names[143][0],	/* SPE rh26.  */			\
-+  &rs6000_reg_names[144][0],	/* SPE rh27.  */			\
-+  &rs6000_reg_names[145][0],	/* SPE rh28.  */			\
-+  &rs6000_reg_names[146][0],	/* SPE rh29.  */			\
-+  &rs6000_reg_names[147][0],	/* SPE rh30.  */			\
-+  &rs6000_reg_names[148][0],	/* SPE rh31.  */			\
- }
- 
- /* Table of additional register names to use in user input.  */
-@@ -2404,7 +2476,17 @@
-   {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104},      \
-   {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108},	\
-   /* Transactional Memory Facility (HTM) Registers.  */		\
--  {"tfhar",  114}, {"tfiar",  115}, {"texasr",  116} }
-+  {"tfhar",  114}, {"tfiar",  115}, {"texasr",  116},		\
-+  /* SPE high registers.  */					\
-+  {"rh0",  117}, {"rh1",  118}, {"rh2",  119}, {"rh3",  120},	\
-+  {"rh4",  121}, {"rh5",  122}, {"rh6",  123}, {"rh7",  124},	\
-+  {"rh8",  125}, {"rh9",  126}, {"rh10", 127}, {"rh11", 128},	\
-+  {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132},	\
-+  {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136},	\
-+  {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140},	\
-+  {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144},	\
-+  {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148},	\
-+}
- 
- /* This is how to output an element of a case-vector that is relative.  */
- 
-diff -Nura gcc-4.9.1.orig/gcc/config/rs6000/rs6000.md gcc-4.9.1/gcc/config/rs6000/rs6000.md
---- gcc-4.9.1.orig/gcc/config/rs6000/rs6000.md	2014-08-05 14:53:37.292498514 -0300
-+++ gcc-4.9.1/gcc/config/rs6000/rs6000.md	2014-08-05 14:58:33.977555904 -0300
-@@ -56,6 +56,8 @@
-    (TFHAR_REGNO			114)
-    (TFIAR_REGNO			115)
-    (TEXASR_REGNO		116)
-+   (FIRST_SPE_HIGH_REGNO	117)
-+   (LAST_SPE_HIGH_REGNO		148)
-   ])
- 
- ;;
-diff -Nura gcc-4.9.1.orig/gcc/testsuite/gcc.target/powerpc/pr60102.c gcc-4.9.1/gcc/testsuite/gcc.target/powerpc/pr60102.c
---- gcc-4.9.1.orig/gcc/testsuite/gcc.target/powerpc/pr60102.c	1969-12-31 21:00:00.000000000 -0300
-+++ gcc-4.9.1/gcc/testsuite/gcc.target/powerpc/pr60102.c	2014-08-05 14:58:13.847873524 -0300
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
-+/* { dg-options "-mcpu=8548 -mspe -mabi=spe -g -mfloat-gprs=double" } */
-+
-+double
-+pr60102 (double x, int m)
-+{
-+  double y;
-+  y =  m % 2 ? x : 1;
-+  return y;
-+}
-diff -Nura gcc-4.9.1.orig/libgcc/config/rs6000/linux-unwind.h gcc-4.9.1/libgcc/config/rs6000/linux-unwind.h
---- gcc-4.9.1.orig/libgcc/config/rs6000/linux-unwind.h	2014-08-05 14:53:48.900892029 -0300
-+++ gcc-4.9.1/libgcc/config/rs6000/linux-unwind.h	2014-08-05 14:58:33.979555972 -0300
-@@ -274,8 +274,8 @@
- #ifdef __SPE__
-   for (i = 14; i < 32; i++)
-     {
--      fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET;
--      fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset
-+      fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET;
-+      fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset
- 	= (long) &regs->vregs - new_cfa + 4 * i;
-     }
- #endif
diff --git a/package/gcc/4.9.1/100-uclibc-conf.patch b/package/gcc/4.9.2/100-uclibc-conf.patch
index d56bf0a194..d56bf0a194 100644
--- a/package/gcc/4.9.1/100-uclibc-conf.patch
+++ b/package/gcc/4.9.2/100-uclibc-conf.patch
diff --git a/package/gcc/4.9.1/301-missing-execinfo_h.patch b/package/gcc/4.9.2/301-missing-execinfo_h.patch
index 00efda24aa..00efda24aa 100644
--- a/package/gcc/4.9.1/301-missing-execinfo_h.patch
+++ b/package/gcc/4.9.2/301-missing-execinfo_h.patch
diff --git a/package/gcc/4.9.1/810-arm-softfloat-libgcc.patch b/package/gcc/4.9.2/810-arm-softfloat-libgcc.patch
index c8cb377d55..c8cb377d55 100644
--- a/package/gcc/4.9.1/810-arm-softfloat-libgcc.patch
+++ b/package/gcc/4.9.2/810-arm-softfloat-libgcc.patch
diff --git a/package/gcc/4.9.1/830-arm_unbreak_armv4t.patch b/package/gcc/4.9.2/830-arm_unbreak_armv4t.patch
index 37f8f2a54d..37f8f2a54d 100644
--- a/package/gcc/4.9.1/830-arm_unbreak_armv4t.patch
+++ b/package/gcc/4.9.2/830-arm_unbreak_armv4t.patch
diff --git a/package/gcc/4.9.1/840-microblaze-enable-dwarf-eh-support.patch b/package/gcc/4.9.2/840-microblaze-enable-dwarf-eh-support.patch
index e116e2b24a..e116e2b24a 100644
--- a/package/gcc/4.9.1/840-microblaze-enable-dwarf-eh-support.patch
+++ b/package/gcc/4.9.2/840-microblaze-enable-dwarf-eh-support.patch
diff --git a/package/gcc/4.9.1/850-libstdcxx-uclibc-c99.patch b/package/gcc/4.9.2/850-libstdcxx-uclibc-c99.patch
index 331cdcb362..331cdcb362 100644
--- a/package/gcc/4.9.1/850-libstdcxx-uclibc-c99.patch
+++ b/package/gcc/4.9.2/850-libstdcxx-uclibc-c99.patch
diff --git a/package/gcc/4.9.1/900-musl-support.patch b/package/gcc/4.9.2/900-musl-support.patch
index 56502b882c..56502b882c 100644
--- a/package/gcc/4.9.1/900-musl-support.patch
+++ b/package/gcc/4.9.2/900-musl-support.patch
diff --git a/package/gcc/4.9.1/powerpc-link-with-math-lib.patch.conditional b/package/gcc/4.9.2/powerpc-link-with-math-lib.patch.conditional
index b7094fe652..b7094fe652 100644
--- a/package/gcc/4.9.1/powerpc-link-with-math-lib.patch.conditional
+++ b/package/gcc/4.9.2/powerpc-link-with-math-lib.patch.conditional
diff --git a/package/gcc/Config.in.host b/package/gcc/Config.in.host
index d96428cf3a..8be3a9a716 100644
--- a/package/gcc/Config.in.host
+++ b/package/gcc/Config.in.host
@@ -125,7 +125,7 @@ config BR2_GCC_VERSION
 	default "4.5.4"     if BR2_GCC_VERSION_4_5_X
 	default "4.7.4"     if BR2_GCC_VERSION_4_7_X
 	default "4.8.3"     if BR2_GCC_VERSION_4_8_X
-	default "4.9.1"     if BR2_GCC_VERSION_4_9_X
+	default "4.9.2"     if BR2_GCC_VERSION_4_9_X
 	default "arc-2014.08" if BR2_GCC_VERSION_4_8_ARC
 
 config BR2_EXTRA_GCC_CONFIG_OPTIONS