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| author | Mark Corbin <mark.corbin@embecosm.com> | 2018-10-21 20:12:01 +0100 |
|---|---|---|
| committer | Thomas Petazzoni <thomas.petazzoni@bootlin.com> | 2019-01-06 14:09:31 +0100 |
| commit | ae99fa6d641c5726f6e3b2dc977ff958fc863a41 (patch) | |
| tree | 78cda7ba57887c1678d0b70aff6229d3633ef98b /arch/Config.in.riscv | |
| parent | 86d0ecf07615ff47a11ca6aa4d6aba908d6f359a (diff) | |
| download | buildroot-ae99fa6d641c5726f6e3b2dc977ff958fc863a41.tar.gz buildroot-ae99fa6d641c5726f6e3b2dc977ff958fc863a41.zip | |
arch: add support for RISC-V 32-bit (riscv32) architecture
This enables a riscv32 system to be built with a Buildroot generated
toolchain (gcc >= 7.x, binutils >= 2.30, glibc only).
This requires a custom version of glibc 2.26 from the riscv-glibc
repository. Note that there are no tags in this repository, so the
glibc version just consists of the 40 character commit id string.
Thanks to Fabrice Bellard for pointing me towards the 32-bit glibc
repository and for providing the necessary patch to get it to build.
Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
Reviewed-by: Matt Weber <matthew.weber@rockwellcollins.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Diffstat (limited to 'arch/Config.in.riscv')
| -rw-r--r-- | arch/Config.in.riscv | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 4361890bf4..097719e846 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -65,14 +65,35 @@ config BR2_RISCV_ISA_CUSTOM_RVC select BR2_RISCV_ISA_RVC endif +choice + prompt "Target Architecture Size" + default BR2_RISCV_64 + +config BR2_RISCV_32 + bool "32-bit" + config BR2_RISCV_64 - bool - default y + bool "64-bit" select BR2_ARCH_IS_64 +endchoice + choice prompt "Target ABI" - default BR2_RISCV_ABI_LP64 + default BR2_RISCV_ABI_ILP32 if !BR2_ARCH_IS_64 + default BR2_RISCV_ABI_LP64 if BR2_ARCH_IS_64 + +config BR2_RISCV_ABI_ILP32 + bool "ilp32" + depends on !BR2_ARCH_IS_64 + +config BR2_RISCV_ABI_ILP32F + bool "ilp32f" + depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF + +config BR2_RISCV_ABI_ILP32D + bool "ilp32d" + depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD config BR2_RISCV_ABI_LP64 bool "lp64" @@ -88,12 +109,16 @@ config BR2_RISCV_ABI_LP64D endchoice config BR2_ARCH + default "riscv32" if !BR2_ARCH_IS_64 default "riscv64" if BR2_ARCH_IS_64 config BR2_ENDIAN default "LITTLE" config BR2_GCC_TARGET_ABI + default "ilp32" if BR2_RISCV_ABI_ILP32 + default "ilp32f" if BR2_RISCV_ABI_ILP32F + default "ilp32d" if BR2_RISCV_ABI_ILP32D default "lp64" if BR2_RISCV_ABI_LP64 default "lp64f" if BR2_RISCV_ABI_LP64F default "lp64d" if BR2_RISCV_ABI_LP64D |
