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* lpc/uart: Support routing of selected LPC interrupts to LinuxBenjamin Herrenschmidt2017-03-031-3/+5
| | | | | | | | | | | | | Each LPC interrupt can be routed to one of 4 lines to the PSI bridge which represent 4 different system interrupts. This allows LPC clients to request as specific target (Linux or OPAL) and makes the LPC core pick a route and configure it appropriately. The UART is updated to properly forward interrupts to Linux if necessary Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/psi/lpc: Handle proper clearing of LPC SerIRQ latch on DD1Benjamin Herrenschmidt2017-02-071-0/+3
| | | | | | | | | | | | | | | | | On DD1, the LPC SerIRQ are latched to 1 in HW but never back to 0, we need an explicit clear after running the handler. (Not before as they are level interrupts, they will be latched again if they are still pending). For now we do that in lpc_dispatch_ser_irqs() but that only works for interrupts routed to OPAL. In order to support routing LPC interrutps to Linux, we need a custom EOI handler that does the clearing of the latch before we do the EOI in the ESB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc: Add routing support for SerIRQsBenjamin Herrenschmidt2016-08-111-0/+3
| | | | | | | | We can route them to any of 4 PSI interrupts. We use the device-tree to determine the default routing Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc: Move LPC instance variables to a private structureBenjamin Herrenschmidt2016-08-111-3/+0
| | | | | | | | Take them out of struct proc_chip and into a private struct lpcm that's local to lpc.c Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc: Add P9 LPC interrupts supportBenjamin Herrenschmidt2016-08-111-0/+7
| | | | | | | | We currently don't exploit the new MUX that allow to spread them around different PSI interrupts, they all go to LPC#0 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Support for Naples LPC serial interruptsBenjamin Herrenschmidt2015-06-191-2/+57
| | | | | | | | | | | | | | | | | | | | | | | This adds support for the HW SerIRQ deserializer of the P8 LPC bridge which is properly wired up on Naples. It also adds support for detecting and reporting LPC error interrupts on all P8s. On most platforms (Rhesus is the exception here due to the way it lets Linux handle the UART interrupts directly), we modify the device-tree to properly represent the LPC controller as a cascaded interrupt-controller and the "interrupts" property of LPC devices to contain the actual LPC interrupt number for the device. We add a mechanism for drivers to register specific LPC interrupts, and a "workaround" for pre-Naples P8 which platforms can use to call all of them for when the external FPGA based deserializer is used. There's also a callback on LPC resets which isn't used yet, we need a bit more work on the general LPC error handling, but it can be done a separate patches. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add xscom_ok() and lpc_ok() to check XSCOM and LPC usabilityBenjamin Herrenschmidt2015-05-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | his primarily checks whether the caller already holds the corresponding locks to avoid re-entrancy in some of the deep error path such as when XSCOM itself triggers an error log. It will be extended in the case of LPC to also handle known HW error states. We use them to avoid queuing/polling in the BT driver and to discard characters in the UART driver. Note: This will not normally involve a loss of log to the UART as the UART driver is also protected by the console suspend mechanism. So this is a safety mechanism only. This fixes issues where the generation of error logs inside the LPC or XSCOM drivers could cause a re-entrancy (via the BT interface) causing deadlocks. Now, the error logs IPMI messages will be queued up and delivered later on the next poll handler. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* sparse: fix fonction declarationsCédric Le Goater2015-02-261-1/+1
| | | | | Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* i2c: Use new timer facility and improve interrupts handlingBenjamin Herrenschmidt2014-11-121-1/+1
| | | | | | | | | | We only poll the masters for the chip that got the interrupt and we improve the running of the timers as well. We user the new TIMER_POLL facility to replace the use of the OPAL poller, which simplifies the code further. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* hw/i2c: i2c driver infrastructure providing device I/ONeelesh Gupta2014-10-271-0/+3
| | | | | | | | | | | | | | This patch adds the generic i2c driver infrastructure to handle multiple i2c master cores present in the system and exposes structures and interfaces for the client to perform I/O on the i2c slave devices. The driver adds the capability to queue multiple requests from client and let clients notified asynchronously after completion. It does that by handling the i2c interrupt or through OPAL poller in the absence of interrupt. Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* occ: Make timeout platform dependentBenjamin Herrenschmidt2014-08-291-1/+1
| | | | | | | | Keep it 0 for open-power platforms where OCC is going to be preloaded, also avoids a annoying 1mn delay on early openpower and bml when there is no OCC firmware to wait for. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Initial commit of Open Source releaseBenjamin Herrenschmidt2014-07-021-0/+95
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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