diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/capp.c | 4 | ||||
| -rw-r--r-- | hw/npu.c | 6 | ||||
| -rw-r--r-- | hw/npu2-hw-procedures.c | 40 | ||||
| -rw-r--r-- | hw/npu2-opencapi.c | 4 | ||||
| -rw-r--r-- | hw/npu2.c | 4 | ||||
| -rw-r--r-- | hw/p7ioc-phb.c | 6 | ||||
| -rw-r--r-- | hw/phb3.c | 244 | ||||
| -rw-r--r-- | hw/phb4.c | 48 | ||||
| -rw-r--r-- | hw/xscom.c | 4 |
9 files changed, 180 insertions, 180 deletions
@@ -175,7 +175,7 @@ int64_t capp_load_ucode(unsigned int chip_id, uint32_t opal_id, } /* 'CAPPULID' in ASCII */ - if ((be64_to_cpu(ucode->eyecatcher) != 0x43415050554C4944) || + if ((be64_to_cpu(ucode->eyecatcher) != 0x43415050554C4944UL) || (be64_to_cpu(ucode->version != 1))) { PHBERR(opal_id, chip_id, index, "CAPP: ucode header invalid\n"); @@ -190,7 +190,7 @@ int64_t capp_load_ucode(unsigned int chip_id, uint32_t opal_id, offset += sizeof(struct capp_ucode_data_hdr) + chunk_count * 8; /* 'CAPPUCOD' in ASCII */ - if (be64_to_cpu(data->hdr.eyecatcher) != 0x4341505055434F44) { + if (be64_to_cpu(data->hdr.eyecatcher) != 0x4341505055434F44UL) { PHBERR(opal_id, chip_id, index, "CAPP: ucode data header invalid:%i\n", offset); @@ -241,10 +241,10 @@ static int64_t npu_dev_cfg_bar_write(struct npu_dev *dev, /* Update BAR base address */ if (offset == pcrf->start) { - bar->base &= 0xffffffff00000000; + bar->base &= 0xffffffff00000000UL; bar->base |= (data & 0xfffffff0); } else { - bar->base &= 0x00000000ffffffff; + bar->base &= 0x00000000ffffffffUL; bar->base |= ((uint64_t)data << 32); PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd); @@ -1052,7 +1052,7 @@ static void assign_mmio_bars(uint32_t gcid, uint32_t xscom, * Link#3-BAR#1: UNASSIGNED */ xscom_write(gcid, xscom + NPU_AT_SCOM_OFFSET + NX_BAR, - 0x0211000043500000); + 0x0211000043500000UL); xscom_read(gcid, npu_link_scom_base(npu_dn, xscom, 0) + NX_MMIO_BAR_0, &mem_start); diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 5214cddc..f50c8b02 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -229,7 +229,7 @@ static bool poll_fence_status(struct npu2_dev *ndev, uint64_t val) for (i = 0; i < 4096; i++) { fs = npu2_read(ndev->npu, NPU2_NTL_CQ_FENCE_STATUS(ndev)); - if ((fs & 0xc000000000000000) == val) + if ((fs & 0xc000000000000000UL) == val) return true; } @@ -269,7 +269,7 @@ uint32_t reset_ntl(struct npu2_dev *ndev) val |= PPC_BIT(8) | PPC_BIT(9); npu2_write(ndev->npu, NPU2_NTL_MISC_CFG1(ndev), val); - if (!poll_fence_status(ndev, 0xc000000000000000)) + if (!poll_fence_status(ndev, 0xc000000000000000UL)) return PROCEDURE_COMPLETE | PROCEDURE_FAILED; return PROCEDURE_NEXT; @@ -311,10 +311,10 @@ static uint32_t reset_ntl_release(struct npu2_dev *ndev) } val = npu2_read(ndev->npu, NPU2_NTL_MISC_CFG1(ndev)); - val &= 0xFFBFFFFFFFFFFFFF; + val &= 0xFFBFFFFFFFFFFFFFUL; npu2_write(ndev->npu, NPU2_NTL_MISC_CFG1(ndev), val); - if (!poll_fence_status(ndev, 0x8000000000000000)) + if (!poll_fence_status(ndev, 0x8000000000000000UL)) return PROCEDURE_COMPLETE | PROCEDURE_FAILED; return PROCEDURE_NEXT; @@ -323,18 +323,18 @@ static uint32_t reset_ntl_release(struct npu2_dev *ndev) static uint32_t reset_ntl_finish(struct npu2_dev *ndev) { /* Credit Setup */ - npu2_write(ndev->npu, NPU2_NTL_CRED_HDR_CREDIT_TX(ndev), 0x0200000000000000); - npu2_write(ndev->npu, NPU2_NTL_PRB_HDR_CREDIT_TX(ndev), 0x0200000000000000); - npu2_write(ndev->npu, NPU2_NTL_ATR_HDR_CREDIT_TX(ndev), 0x0200000000000000); - npu2_write(ndev->npu, NPU2_NTL_RSP_HDR_CREDIT_TX(ndev), 0x0200000000000000); - npu2_write(ndev->npu, NPU2_NTL_CRED_DATA_CREDIT_TX(ndev), 0x1000000000000000); - npu2_write(ndev->npu, NPU2_NTL_RSP_DATA_CREDIT_TX(ndev), 0x1000000000000000); - npu2_write(ndev->npu, NPU2_NTL_CRED_HDR_CREDIT_RX(ndev), 0x0000BE0000000000); - npu2_write(ndev->npu, NPU2_NTL_DBD_HDR_CREDIT_RX(ndev), 0x0000640000000000); - npu2_write(ndev->npu, NPU2_NTL_ATSD_HDR_CREDIT_RX(ndev), 0x0000200000000000); - npu2_write(ndev->npu, NPU2_NTL_RSP_HDR_CREDIT_RX(ndev), 0x0000BE0000000000); - npu2_write(ndev->npu, NPU2_NTL_CRED_DATA_CREDIT_RX(ndev), 0x0001000000000000); - npu2_write(ndev->npu, NPU2_NTL_RSP_DATA_CREDIT_RX(ndev), 0x0001000000000000); + npu2_write(ndev->npu, NPU2_NTL_CRED_HDR_CREDIT_TX(ndev), 0x0200000000000000UL); + npu2_write(ndev->npu, NPU2_NTL_PRB_HDR_CREDIT_TX(ndev), 0x0200000000000000UL); + npu2_write(ndev->npu, NPU2_NTL_ATR_HDR_CREDIT_TX(ndev), 0x0200000000000000UL); + npu2_write(ndev->npu, NPU2_NTL_RSP_HDR_CREDIT_TX(ndev), 0x0200000000000000UL); + npu2_write(ndev->npu, NPU2_NTL_CRED_DATA_CREDIT_TX(ndev), 0x1000000000000000UL); + npu2_write(ndev->npu, NPU2_NTL_RSP_DATA_CREDIT_TX(ndev), 0x1000000000000000UL); + npu2_write(ndev->npu, NPU2_NTL_CRED_HDR_CREDIT_RX(ndev), 0x0000BE0000000000UL); + npu2_write(ndev->npu, NPU2_NTL_DBD_HDR_CREDIT_RX(ndev), 0x0000640000000000UL); + npu2_write(ndev->npu, NPU2_NTL_ATSD_HDR_CREDIT_RX(ndev), 0x0000200000000000UL); + npu2_write(ndev->npu, NPU2_NTL_RSP_HDR_CREDIT_RX(ndev), 0x0000BE0000000000UL); + npu2_write(ndev->npu, NPU2_NTL_CRED_DATA_CREDIT_RX(ndev), 0x0001000000000000UL); + npu2_write(ndev->npu, NPU2_NTL_RSP_DATA_CREDIT_RX(ndev), 0x0001000000000000UL); npu2_set_link_flag(ndev, NPU2_DEV_DL_RESET); @@ -396,12 +396,12 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev) phy_write(ndev, &NPU2_PHY_RX_AC_COUPLED, 1); switch (ndev->link_speed) { - case 20000000000: + case 20000000000UL: prlog(PR_INFO, "OCAPI: Link speed set at 20Gb/s\n"); phy_write(ndev, &NPU2_PHY_RX_SPEED_SELECT, 1); break; - case 25000000000: - case 25781250000: + case 25000000000UL: + case 25781250000UL: prlog(PR_INFO, "OCAPI: Link speed set at 25.xGb/s\n"); phy_write(ndev, &NPU2_PHY_RX_SPEED_SELECT, 0); break; @@ -770,7 +770,7 @@ static uint32_t check_credits(struct npu2_dev *ndev) assert(!fail); val = npu2_read(ndev->npu, NPU2_NTL_MISC_CFG1(ndev)); - val &= 0xFF3FFFFFFFFFFFFF; + val &= 0xFF3FFFFFFFFFFFFFUL; npu2_write(ndev->npu, NPU2_NTL_MISC_CFG1(ndev), val); if (!poll_fence_status(ndev, 0x0)) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index 8075d4e5..aa3c434e 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -711,7 +711,7 @@ static void address_translation_config(uint32_t gcid, uint32_t scom_base, /* To update XSL_GP, we must first write a magic value to it */ npu2_scom_write(gcid, scom_base, NPU2_REG_OFFSET(stack, NPU2_BLOCK_XSL, NPU2_XSL_GP), - NPU2_MISC_DA_LEN_8B, 0x0523790323000000); + NPU2_MISC_DA_LEN_8B, 0x0523790323000000UL); reg &= ~NPU2_XSL_GP_BLOOM_FILTER_ENABLE; npu2_scom_write(gcid, scom_base, NPU2_REG_OFFSET(stack, NPU2_BLOCK_XSL, NPU2_XSL_GP), @@ -722,7 +722,7 @@ static void address_translation_config(uint32_t gcid, uint32_t scom_base, /* * DD2.0/2.1 EOA Bug. Fixed in DD2.2 */ - reg = 0x32F8000000000001; + reg = 0x32F8000000000001UL; npu2_scom_write(gcid, scom_base, NPU2_REG_OFFSET(stack, NPU2_BLOCK_XSL, NPU2_XSL_DEF), @@ -283,10 +283,10 @@ static int64_t npu2_cfg_write_bar(struct npu2_dev *dev, } if (offset == pcrf->start) { - npu2_bar->base &= 0xffffffff00000000; + npu2_bar->base &= 0xffffffff00000000UL; npu2_bar->base |= (data & 0xfffffff0); } else { - npu2_bar->base &= 0x00000000ffffffff; + npu2_bar->base &= 0x00000000ffffffffUL; npu2_bar->base |= ((uint64_t)data << 32); if (NPU2_REG(npu2_bar->reg) == NPU2_GENID_BAR && NPU2DEV_BRICK(dev)) diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c index e8730f48..33de10ad 100644 --- a/hw/p7ioc-phb.c +++ b/hw/p7ioc-phb.c @@ -1973,7 +1973,7 @@ static void p7ioc_prepare_link_change(struct pci_slot *slot, bool up) if (!up) { /* Mask PCIE port interrupts and AER receiver error */ - out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7E00000000000000); + out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7E00000000000000UL); p7ioc_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_MASK, &cfg32); cfg32 |= PCIECAP_AER_CE_RECVR_ERR; @@ -1992,8 +1992,8 @@ static void p7ioc_prepare_link_change(struct pci_slot *slot, bool up) p->flags |= P7IOC_PHB_CFG_BLOCKED; } else { /* Clear spurious errors and enable PCIE port interrupts */ - out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0x00E0000000000000); - out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xFE65000000000000); + out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0x00E0000000000000UL); + out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xFE65000000000000UL); /* Clear AER receiver error status */ p7ioc_pcicfg_write32(&p->phb, 0, @@ -395,7 +395,7 @@ static void phb3_root_port_init(struct phb *phb, struct pci_device *dev, * instead of EEH subsystem. */ if (dev->slot && dev->slot->surprise_pluggable) - out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad42800000000000); + out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad42800000000000UL); /* Enable SERR and parity checking */ pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16); @@ -1426,11 +1426,11 @@ static bool phb3_err_check_pbcq(struct phb3 *p) uint64_t nfir, mask, wof, val64; int32_t class, bit; uint64_t severity[PHB3_ERR_CLASS_LAST] = { - 0x0000000000000000, /* NONE */ - 0x018000F800000000, /* DEAD */ - 0x7E7DC70000000000, /* FENCED */ - 0x0000000000000000, /* ER */ - 0x0000000000000000 /* INF */ + 0x0000000000000000UL, /* NONE */ + 0x018000F800000000UL, /* DEAD */ + 0x7E7DC70000000000UL, /* FENCED */ + 0x0000000000000000UL, /* ER */ + 0x0000000000000000UL /* INF */ }; /* @@ -1439,7 +1439,7 @@ static bool phb3_err_check_pbcq(struct phb3 *p) * into account any more. */ xscom_read(p->chip_id, p->pe_xscom + 0x0, &nfir); - if (nfir == 0xffffffffffffffff) { + if (nfir == 0xffffffffffffffffUL) { p->err.err_src = PHB3_ERR_SRC_NONE; p->err.err_class = PHB3_ERR_CLASS_DEAD; phb3_set_err_pending(p, true); @@ -1491,11 +1491,11 @@ static bool phb3_err_check_lem(struct phb3 *p) uint64_t fir, wof, mask, val64; int32_t class, bit; uint64_t severity[PHB3_ERR_CLASS_LAST] = { - 0x0000000000000000, /* NONE */ - 0x0000000000000000, /* DEAD */ - 0xADB670C980ADD151, /* FENCED */ - 0x000800107F500A2C, /* ER */ - 0x42018E2200002482 /* INF */ + 0x0000000000000000UL, /* NONE */ + 0x0000000000000000UL, /* DEAD */ + 0xADB670C980ADD151UL, /* FENCED */ + 0x000800107F500A2CUL, /* ER */ + 0x42018E2200002482UL /* INF */ }; /* @@ -1503,7 +1503,7 @@ static bool phb3_err_check_lem(struct phb3 *p) * go forward and just mark the PHB with dead state */ fir = phb3_read_reg_asb(p, PHB_LEM_FIR_ACCUM); - if (fir == 0xffffffffffffffff) { + if (fir == 0xffffffffffffffffUL) { p->err.err_src = PHB3_ERR_SRC_PHB; p->err.err_class = PHB3_ERR_CLASS_DEAD; phb3_set_err_pending(p, true); @@ -2111,7 +2111,7 @@ static void phb3_prepare_link_change(struct pci_slot *slot, if (!pd || !pd->slot || !pd->slot->surprise_pluggable) { /* Mask PCIE port interrupts */ out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, - 0xad42800000000000); + 0xad42800000000000UL); pci_cfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_MASK, ®32); @@ -2144,11 +2144,11 @@ static void phb3_prepare_link_change(struct pci_slot *slot, /* Clear spurrious errors and enable PCIE port interrupts */ out_be64(p->regs + UTL_PCIE_PORT_STATUS, - 0xffdfffffffffffff); + 0xffdfffffffffffffUL); if (!pd || !pd->slot || !pd->slot->surprise_pluggable) { out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, - 0xad52800000000000); + 0xad52800000000000UL); pci_cfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_MASK, ®32); @@ -2439,7 +2439,7 @@ static int64_t load_capp_ucode(struct phb3 *p) /* 0x434150504c494448 = 'CAPPLIDH' in ASCII */ rc = capp_load_ucode(p->chip_id, p->phb.opal_id, p->index, - 0x434150504c494448, PHB3_CAPP_REG_OFFSET(p), + 0x434150504c494448UL, PHB3_CAPP_REG_OFFSET(p), CAPP_APC_MASTER_ARRAY_ADDR_REG, CAPP_APC_MASTER_ARRAY_WRITE_REG, CAPP_SNP_ARRAY_ADDR_REG, @@ -2546,7 +2546,7 @@ static void disable_capi_mode(struct phb3 *p) xscom_write(p->chip_id, p->pci_xscom + 0xd, reg); /* AIB TX Credit Init Timer - reset timer */ - xscom_write(p->chip_id, p->pci_xscom + 0xc, 0xff00000000000000); + xscom_write(p->chip_id, p->pci_xscom + 0xc, 0xff00000000000000UL); /* * PBCQ Mode Control Register - set dcache handling to normal, not CAPP @@ -2559,7 +2559,7 @@ static void disable_capi_mode(struct phb3 *p) /* Registers touched by phb3_init_capp_regs() */ /* CAPP Transport Control Register */ - xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, 0x0001000000000000); + xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, 0x0001000000000000UL); /* Canned pResp Map Register 0/1/2 */ xscom_write(p->chip_id, CANNED_PRESP_MAP0 + offset, 0); @@ -2624,7 +2624,7 @@ static int64_t phb3_creset(struct pci_slot *slot) xscom_read(p->chip_id, p->spci_xscom + 1, &val);/* HW275117 */ xscom_write(p->chip_id, p->pci_xscom + 0xa, - 0x8000000000000000); + 0x8000000000000000UL); pci_slot_set_state(slot, PHB3_SLOT_CRESET_WAIT_CQ); slot->retries = 500; return pci_slot_set_sm_timeout(slot, msecs_to_tb(10)); @@ -2633,7 +2633,7 @@ static int64_t phb3_creset(struct pci_slot *slot) xscom_read(p->chip_id, p->pe_xscom + 0x1d, &val); xscom_read(p->chip_id, p->pe_xscom + 0x1e, &val); xscom_read(p->chip_id, p->pe_xscom + 0xf, &cqsts); - if (!(cqsts & 0xC000000000000000)) { + if (!(cqsts & 0xC000000000000000UL)) { PHBDBG(p, "CRESET: No pending transactions\n"); xscom_write(p->chip_id, p->pe_xscom + 0x1, ~p->nfir_cache); @@ -2794,7 +2794,7 @@ static int64_t phb3_eeh_freeze_clear(struct phb *phb, uint64_t pe_number, * explicitely by the user */ err = in_be64(p->regs + PHB_ETU_ERR_SUMMARY); - if (err == 0xffffffffffffffff) { + if (err == 0xffffffffffffffffUL) { if (phb3_fenced(p)) { PHBERR(p, "eeh_freeze_clear on fenced PHB\n"); return OPAL_HARDWARE; @@ -3475,29 +3475,29 @@ static void phb3_init_capp_regs(struct phb3 *p, bool dma_mode) * CAPP1/PHB1 -> APC MASTER(bits 1:3) = 0b010 */ reg = 0x4000000000000000ULL >> p->index; - reg |= 0x0070000000000000; + reg |= 0x0070000000000000UL; xscom_write(p->chip_id, APC_MASTER_CAPI_CTRL + offset, reg); PHBINF(p, "CAPP: port attached\n"); /* tlb and mmio */ - xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, 0x4028000104000000); + xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, 0x4028000104000000UL); xscom_write(p->chip_id, CANNED_PRESP_MAP0 + offset, 0); - xscom_write(p->chip_id, CANNED_PRESP_MAP1 + offset, 0xFFFFFFFF00000000); + xscom_write(p->chip_id, CANNED_PRESP_MAP1 + offset, 0xFFFFFFFF00000000UL); xscom_write(p->chip_id, CANNED_PRESP_MAP2 + offset, 0); /* error recovery */ xscom_write(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, 0); xscom_write(p->chip_id, FLUSH_SUE_STATE_MAP + offset, - 0x1DC20B6600000000); + 0x1DC20B6600000000UL); xscom_write(p->chip_id, CAPP_EPOCH_TIMER_CTRL + offset, - 0xC0000000FFF0FFE0); + 0xC0000000FFF0FFE0UL); xscom_write(p->chip_id, FLUSH_UOP_CONFIG1 + offset, - 0xB188280728000000); - xscom_write(p->chip_id, FLUSH_UOP_CONFIG2 + offset, 0xB188400F00000000); + 0xB188280728000000UL); + xscom_write(p->chip_id, FLUSH_UOP_CONFIG2 + offset, 0xB188400F00000000UL); - reg = 0xA1F0000000000000; + reg = 0xA1F0000000000000UL; reg |= read_buffers << PPC_BITLSHIFT(39); xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, reg); } @@ -3505,11 +3505,11 @@ static void phb3_init_capp_regs(struct phb3 *p, bool dma_mode) /* override some inits with CAPI defaults */ static void phb3_init_capp_errors(struct phb3 *p) { - out_be64(p->regs + PHB_ERR_AIB_FENCE_ENABLE, 0xffffffdd8c80ffc0); - out_be64(p->regs + PHB_OUT_ERR_AIB_FENCE_ENABLE, 0x9cf3fe08f8dc700f); - out_be64(p->regs + PHB_INA_ERR_AIB_FENCE_ENABLE, 0xffff57fbff01ffde); - out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0xfcffe0fbff7ff0ec); - out_be64(p->regs + PHB_LEM_ERROR_MASK, 0x40018e2400022482); + out_be64(p->regs + PHB_ERR_AIB_FENCE_ENABLE, 0xffffffdd8c80ffc0UL); + out_be64(p->regs + PHB_OUT_ERR_AIB_FENCE_ENABLE, 0x9cf3fe08f8dc700fUL); + out_be64(p->regs + PHB_INA_ERR_AIB_FENCE_ENABLE, 0xffff57fbff01ffdeUL); + out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0xfcffe0fbff7ff0ecUL); + out_be64(p->regs + PHB_LEM_ERROR_MASK, 0x40018e2400022482UL); } /* @@ -3530,11 +3530,11 @@ static int64_t enable_capi_mode(struct phb3 *p, uint64_t pe_number, bool dma_mod /* poll cqstat */ for (i = 0; i < 500000; i++) { xscom_read(p->chip_id, p->pe_xscom + 0xf, ®); - if (!(reg & 0xC000000000000000)) + if (!(reg & 0xC000000000000000UL)) break; time_wait_us(10); } - if (reg & 0xC000000000000000) { + if (reg & 0xC000000000000000UL) { PHBERR(p, "CAPP: Timeout waiting for pending transaction\n"); return OPAL_HARDWARE; } @@ -3714,7 +3714,7 @@ static int64_t phb3_set_capi_mode(struct phb *phb, uint64_t mode, */ xscom_read(p->chip_id, APC_MASTER_PB_CTRL + offset, ®); read_buffers = (reg >> PPC_BITLSHIFT(11)) & 0x3; - reg = 0xA1F0000000000000; + reg = 0xA1F0000000000000UL; reg |= read_buffers << PPC_BITLSHIFT(39); xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, reg); @@ -3783,28 +3783,28 @@ static const struct phb_ops phb3_ops = { static void phb3_setup_aib(struct phb3 *p) { /* Init_2 - AIB TX Channel Mapping Register */ - phb3_write_reg_asb(p, PHB_AIB_TX_CHAN_MAPPING, 0x0211230000000000); + phb3_write_reg_asb(p, PHB_AIB_TX_CHAN_MAPPING, 0x0211230000000000UL); /* Init_3 - AIB RX command credit register */ if (p->rev >= PHB3_REV_VENICE_DD20) - phb3_write_reg_asb(p, PHB_AIB_RX_CMD_CRED, 0x0020000100020001); + phb3_write_reg_asb(p, PHB_AIB_RX_CMD_CRED, 0x0020000100020001UL); else - phb3_write_reg_asb(p, PHB_AIB_RX_CMD_CRED, 0x0020000100010001); + phb3_write_reg_asb(p, PHB_AIB_RX_CMD_CRED, 0x0020000100010001UL); /* Init_4 - AIB rx data credit register */ if (p->rev >= PHB3_REV_VENICE_DD20) - phb3_write_reg_asb(p, PHB_AIB_RX_DATA_CRED, 0x0020002000010001); + phb3_write_reg_asb(p, PHB_AIB_RX_DATA_CRED, 0x0020002000010001UL); else - phb3_write_reg_asb(p, PHB_AIB_RX_DATA_CRED, 0x0020002000000001); + phb3_write_reg_asb(p, PHB_AIB_RX_DATA_CRED, 0x0020002000000001UL); /* Init_5 - AIB rx credit init timer register */ - phb3_write_reg_asb(p, PHB_AIB_RX_CRED_INIT_TIMER, 0x0f00000000000000); + phb3_write_reg_asb(p, PHB_AIB_RX_CRED_INIT_TIMER, 0x0f00000000000000UL); /* Init_6 - AIB Tag Enable register */ - phb3_write_reg_asb(p, PHB_AIB_TAG_ENABLE, 0xffffffff00000000); + phb3_write_reg_asb(p, PHB_AIB_TAG_ENABLE, 0xffffffff00000000UL); /* Init_7 - TCE Tag Enable register */ - phb3_write_reg_asb(p, PHB_TCE_TAG_ENABLE, 0xffffffff00000000); + phb3_write_reg_asb(p, PHB_TCE_TAG_ENABLE, 0xffffffff00000000UL); } static void phb3_init_ioda2(struct phb3 *p) @@ -3850,9 +3850,9 @@ static void phb3_init_ioda2(struct phb3 *p) * The register doesn't take effect on Murano DD1.0 */ if (p->rev >= PHB3_REV_NAPLES_DD10) - out_be64(p->regs + PHB_INTREP_TIMER, 0x0014000000000000); + out_be64(p->regs + PHB_INTREP_TIMER, 0x0014000000000000UL); else if (p->rev >= PHB3_REV_MURANO_DD20) - out_be64(p->regs + PHB_INTREP_TIMER, 0x0004000000000000); + out_be64(p->regs + PHB_INTREP_TIMER, 0x0004000000000000UL); else out_be64(p->regs + PHB_INTREP_TIMER, 0); @@ -4054,9 +4054,9 @@ static void phb3_init_utl(struct phb3 *p) /* Init_77..79: Clear spurrious errors and assign errors to the * right "interrupt" signal */ - out_be64(p->regs + UTL_SYS_BUS_AGENT_STATUS, 0xffffffffffffffff); - out_be64(p->regs + UTL_SYS_BUS_AGENT_ERR_SEVERITY, 0x5000000000000000); - out_be64(p->regs + UTL_SYS_BUS_AGENT_IRQ_EN, 0xfcc0000000000000); + out_be64(p->regs + UTL_SYS_BUS_AGENT_STATUS, 0xffffffffffffffffUL); + out_be64(p->regs + UTL_SYS_BUS_AGENT_ERR_SEVERITY, 0x5000000000000000UL); + out_be64(p->regs + UTL_SYS_BUS_AGENT_IRQ_EN, 0xfcc0000000000000UL); /* Init_80..81: Setup tag allocations * @@ -4066,66 +4066,66 @@ static void phb3_init_utl(struct phb3 *p) /* Init_82: PCI Express port control * SW283991: Set Outbound Non-Posted request timeout to 16ms (RTOS). */ - out_be64(p->regs + UTL_PCIE_PORT_CONTROL, 0x8588007000000000); + out_be64(p->regs + UTL_PCIE_PORT_CONTROL, 0x8588007000000000UL); /* Init_83..85: Clean & setup port errors */ - out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xffdfffffffffffff); - out_be64(p->regs + UTL_PCIE_PORT_ERROR_SEV, 0x5039000000000000); + out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xffdfffffffffffffUL); + out_be64(p->regs + UTL_PCIE_PORT_ERROR_SEV, 0x5039000000000000UL); if (p->has_link) - out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad52800000000000); + out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad52800000000000UL); else - out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad42800000000000); + out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad42800000000000UL); /* Init_86 : Cleanup RC errors */ - out_be64(p->regs + UTL_RC_STATUS, 0xffffffffffffffff); + out_be64(p->regs + UTL_RC_STATUS, 0xffffffffffffffffUL); } static void phb3_init_errors(struct phb3 *p) { /* Init_88: LEM Error Mask : Temporarily disable error interrupts */ - out_be64(p->regs + PHB_LEM_ERROR_MASK, 0xffffffffffffffff); + out_be64(p->regs + PHB_LEM_ERROR_MASK, 0xffffffffffffffffUL); /* Init_89..97: Disable all error interrupts until end of init */ - out_be64(p->regs + PHB_ERR_STATUS, 0xffffffffffffffff); - out_be64(p->regs + PHB_ERR1_STATUS, 0x0000000000000000); - out_be64(p->regs + PHB_ERR_LEM_ENABLE, 0xffffffffffffffff); - out_be64(p->regs + PHB_ERR_FREEZE_ENABLE, 0x0000000080800000); - out_be64(p->regs + PHB_ERR_AIB_FENCE_ENABLE, 0xffffffdd0c00ffc0); - out_be64(p->regs + PHB_ERR_LOG_0, 0x0000000000000000); - out_be64(p->regs + PHB_ERR_LOG_1, 0x0000000000000000); - out_be64(p->regs + PHB_ERR_STATUS_MASK, 0x0000000000000000); - out_be64(p->regs + PHB_ERR1_STATUS_MASK, 0x0000000000000000); + out_be64(p->regs + PHB_ERR_STATUS, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_ERR1_STATUS, 0x0000000000000000UL); + out_be64(p->regs + PHB_ERR_LEM_ENABLE, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_ERR_FREEZE_ENABLE, 0x0000000080800000UL); + out_be64(p->regs + PHB_ERR_AIB_FENCE_ENABLE, 0xffffffdd0c00ffc0UL); + out_be64(p->regs + PHB_ERR_LOG_0, 0x0000000000000000UL); + out_be64(p->regs + PHB_ERR_LOG_1, 0x0000000000000000UL); + out_be64(p->regs + PHB_ERR_STATUS_MASK, 0x0000000000000000UL); + out_be64(p->regs + PHB_ERR1_STATUS_MASK, 0x0000000000000000UL); /* Init_98_106: Configure MMIO error traps & clear old state * * Don't enable BAR multi-hit detection in bit 41. */ - out_be64(p->regs + PHB_OUT_ERR_STATUS, 0xffffffffffffffff); - out_be64(p->regs + PHB_OUT_ERR1_STATUS, 0x0000000000000000); - out_be64(p->regs + PHB_OUT_ERR_LEM_ENABLE, 0xfdffffffffbfffff); - out_be64(p->regs + PHB_OUT_ERR_FREEZE_ENABLE, 0x0000420800000000); - out_be64(p->regs + PHB_OUT_ERR_AIB_FENCE_ENABLE, 0x9cf3bc00f89c700f); - out_be64(p->regs + PHB_OUT_ERR_LOG_0, 0x0000000000000000); - out_be64(p->regs + PHB_OUT_ERR_LOG_1, 0x0000000000000000); - out_be64(p->regs + PHB_OUT_ERR_STATUS_MASK, 0x0000000000400000); - out_be64(p->regs + PHB_OUT_ERR1_STATUS_MASK, 0x0000000000400000); + out_be64(p->regs + PHB_OUT_ERR_STATUS, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_OUT_ERR1_STATUS, 0x0000000000000000UL); + out_be64(p->regs + PHB_OUT_ERR_LEM_ENABLE, 0xfdffffffffbfffffUL); + out_be64(p->regs + PHB_OUT_ERR_FREEZE_ENABLE, 0x0000420800000000UL); + out_be64(p->regs + PHB_OUT_ERR_AIB_FENCE_ENABLE, 0x9cf3bc00f89c700fUL); + out_be64(p->regs + PHB_OUT_ERR_LOG_0, 0x0000000000000000UL); + out_be64(p->regs + PHB_OUT_ERR_LOG_1, 0x0000000000000000UL); + out_be64(p->regs + PHB_OUT_ERR_STATUS_MASK, 0x0000000000400000UL); + out_be64(p->regs + PHB_OUT_ERR1_STATUS_MASK, 0x0000000000400000UL); /* Init_107_115: Configure DMA_A error traps & clear old state */ - out_be64(p->regs + PHB_INA_ERR_STATUS, 0xffffffffffffffff); - out_be64(p->regs + PHB_INA_ERR1_STATUS, 0x0000000000000000); - out_be64(p->regs + PHB_INA_ERR_LEM_ENABLE, 0xffffffffffffffff); - out_be64(p->regs + PHB_INA_ERR_FREEZE_ENABLE, 0xc00003a901006000); - out_be64(p->regs + PHB_INA_ERR_AIB_FENCE_ENABLE, 0x3fff5452fe019fde); - out_be64(p->regs + PHB_INA_ERR_LOG_0, 0x0000000000000000); - out_be64(p->regs + PHB_INA_ERR_LOG_1, 0x0000000000000000); - out_be64(p->regs + PHB_INA_ERR_STATUS_MASK, 0x0000000000000000); - out_be64(p->regs + PHB_INA_ERR1_STATUS_MASK, 0x0000000000000000); + out_be64(p->regs + PHB_INA_ERR_STATUS, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_INA_ERR1_STATUS, 0x0000000000000000UL); + out_be64(p->regs + PHB_INA_ERR_LEM_ENABLE, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_INA_ERR_FREEZE_ENABLE, 0xc00003a901006000UL); + out_be64(p->regs + PHB_INA_ERR_AIB_FENCE_ENABLE, 0x3fff5452fe019fdeUL); + out_be64(p->regs + PHB_INA_ERR_LOG_0, 0x0000000000000000UL); + out_be64(p->regs + PHB_INA_ERR_LOG_1, 0x0000000000000000UL); + out_be64(p->regs + PHB_INA_ERR_STATUS_MASK, 0x0000000000000000UL); + out_be64(p->regs + PHB_INA_ERR1_STATUS_MASK, 0x0000000000000000UL); /* Init_116_124: Configure DMA_B error traps & clear old state */ - out_be64(p->regs + PHB_INB_ERR_STATUS, 0xffffffffffffffff); - out_be64(p->regs + PHB_INB_ERR1_STATUS, 0x0000000000000000); - out_be64(p->regs + PHB_INB_ERR_LEM_ENABLE, 0xffffffffffffffff); + out_be64(p->regs + PHB_INB_ERR_STATUS, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_INB_ERR1_STATUS, 0x0000000000000000UL); + out_be64(p->regs + PHB_INB_ERR_LEM_ENABLE, 0xffffffffffffffffUL); /* * Workaround for errata HW257476, turn correctable messages into @@ -4133,22 +4133,22 @@ static void phb3_init_errors(struct phb3 *p) */ if (p->rev < PHB3_REV_MURANO_DD20) out_be64(p->regs + PHB_INB_ERR_FREEZE_ENABLE, - 0x0000600000000070); + 0x0000600000000070UL); else out_be64(p->regs + PHB_INB_ERR_FREEZE_ENABLE, - 0x0000600000000060); + 0x0000600000000060UL); - out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0xfcff80fbff7ff08c); - out_be64(p->regs + PHB_INB_ERR_LOG_0, 0x0000000000000000); - out_be64(p->regs + PHB_INB_ERR_LOG_1, 0x0000000000000000); - out_be64(p->regs + PHB_INB_ERR_STATUS_MASK, 0x0000000000000000); - out_be64(p->regs + PHB_INB_ERR1_STATUS_MASK, 0x0000000000000000); + out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0xfcff80fbff7ff08cUL); + out_be64(p->regs + PHB_INB_ERR_LOG_0, 0x0000000000000000UL); + out_be64(p->regs + PHB_INB_ERR_LOG_1, 0x0000000000000000UL); + out_be64(p->regs + PHB_INB_ERR_STATUS_MASK, 0x0000000000000000UL); + out_be64(p->regs + PHB_INB_ERR1_STATUS_MASK, 0x0000000000000000UL); /* Init_125..128: Cleanup & configure LEM */ - out_be64(p->regs + PHB_LEM_FIR_ACCUM, 0x0000000000000000); - out_be64(p->regs + PHB_LEM_ACTION0, 0xffffffffffffffff); - out_be64(p->regs + PHB_LEM_ACTION1, 0xffffffffffffffff); - out_be64(p->regs + PHB_LEM_WOF, 0x0000000000000000); + out_be64(p->regs + PHB_LEM_FIR_ACCUM, 0x0000000000000000UL); + out_be64(p->regs + PHB_LEM_ACTION0, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_LEM_ACTION1, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_LEM_WOF, 0x0000000000000000UL); } static int64_t phb3_fixup_pec_inits(struct phb3 *p) @@ -4198,7 +4198,7 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) /* Grab version and fit it in an int */ val = phb3_read_reg_asb(p, PHB_VERSION); - if (val == 0 || val == 0xffffffffffffffff) { + if (val == 0 || val == 0xffffffffffffffffUL) { PHBERR(p, "Failed to read version, PHB appears broken\n"); goto failed; } @@ -4243,7 +4243,7 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) * and Venice */ if (p->index == 2 && p->rev < PHB3_REV_NAPLES_DD10) - out_be64(p->regs + PHB_PCIE_SYS_LINK_INIT, 0x9008133332120000); + out_be64(p->regs + PHB_PCIE_SYS_LINK_INIT, 0x9008133332120000UL); /* Init_13 - PCIE Reset */ /* @@ -4251,25 +4251,25 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) * later by the initial PERST state machine */ PHBDBG(p, "PHB_RESET is 0x%016llx\n", in_be64(p->regs + PHB_RESET)); - out_be64(p->regs + PHB_RESET, 0xd000000000000000); + out_be64(p->regs + PHB_RESET, 0xd000000000000000UL); /* Architected IODA2 inits */ phb3_init_ioda2(p); /* Init_37..42 - Clear UTL & DLP error logs */ - out_be64(p->regs + PHB_PCIE_UTL_ERRLOG1, 0xffffffffffffffff); - out_be64(p->regs + PHB_PCIE_UTL_ERRLOG2, 0xffffffffffffffff); - out_be64(p->regs + PHB_PCIE_UTL_ERRLOG3, 0xffffffffffffffff); - out_be64(p->regs + PHB_PCIE_UTL_ERRLOG4, 0xffffffffffffffff); - out_be64(p->regs + PHB_PCIE_DLP_ERRLOG1, 0xffffffffffffffff); - out_be64(p->regs + PHB_PCIE_DLP_ERRLOG2, 0xffffffffffffffff); + out_be64(p->regs + PHB_PCIE_UTL_ERRLOG1, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_PCIE_UTL_ERRLOG2, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_PCIE_UTL_ERRLOG3, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_PCIE_UTL_ERRLOG4, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_PCIE_DLP_ERRLOG1, 0xffffffffffffffffUL); + out_be64(p->regs + PHB_PCIE_DLP_ERRLOG2, 0xffffffffffffffffUL); /* Init_43 - Wait for UTL core to come out of reset */ if (!phb3_wait_dlp_reset(p)) goto failed; /* Init_44 - Clear port status */ - out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xffffffffffffffff); + out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xffffffffffffffffUL); /* Init_45..76: Init root complex config space */ if (!phb3_init_rc_cfg(p)) @@ -4283,17 +4283,17 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) * Enable IVC for Murano DD2.0 or later one */ #ifdef IVT_TABLE_IVE_16B - val = 0xf3a80e4b00000000; + val = 0xf3a80e4b00000000UL; #else - val = 0xf3a80ecb00000000; + val = 0xf3a80ecb00000000UL; #endif if (p->rev >= PHB3_REV_MURANO_DD20) - val |= 0x0000010000000000; + val |= 0x0000010000000000UL; if (first_init && p->rev >= PHB3_REV_NAPLES_DD10) { /* Enable 32-bit bypass support on Naples and tell the OS * about it */ - val |= 0x0010000000000000; + val |= 0x0010000000000000UL; dt_add_property(p->phb.dt_node, "ibm,32-bit-bypass-supported", NULL, 0); } @@ -4338,11 +4338,11 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) /* Init_136 - Re-enable error interrupts */ /* TBD: Should we mask any of these for PERST ? */ - out_be64(p->regs + PHB_ERR_IRQ_ENABLE, 0x0000002280b80000); - out_be64(p->regs + PHB_OUT_ERR_IRQ_ENABLE, 0x600c42fc042080f0); - out_be64(p->regs + PHB_INA_ERR_IRQ_ENABLE, 0xc000a3a901826020); - out_be64(p->regs + PHB_INB_ERR_IRQ_ENABLE, 0x0000600000800070); - out_be64(p->regs + PHB_LEM_ERROR_MASK, 0x42498e367f502eae); + out_be64(p->regs + PHB_ERR_IRQ_ENABLE, 0x0000002280b80000UL); + out_be64(p->regs + PHB_OUT_ERR_IRQ_ENABLE, 0x600c42fc042080f0UL); + out_be64(p->regs + PHB_INA_ERR_IRQ_ENABLE, 0xc000a3a901826020UL); + out_be64(p->regs + PHB_INB_ERR_IRQ_ENABLE, 0x0000600000800070UL); + out_be64(p->regs + PHB_LEM_ERROR_MASK, 0x42498e367f502eaeUL); /* * Init_141 - Enable DMA address speculation @@ -4354,21 +4354,21 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) * it once that has been done. */ if (p->rev >= PHB3_REV_MURANO_DD20) - out_be64(p->regs + PHB_TCE_SPEC_CTL, 0xf000000000000000); + out_be64(p->regs + PHB_TCE_SPEC_CTL, 0xf000000000000000UL); else out_be64(p->regs + PHB_TCE_SPEC_CTL, 0x0ul); /* Errata#20131017: avoid TCE queue overflow */ if (p->rev == PHB3_REV_MURANO_DD20) - phb3_write_reg_asb(p, PHB_TCE_WATERMARK, 0x0003000000030302); + phb3_write_reg_asb(p, PHB_TCE_WATERMARK, 0x0003000000030302UL); /* Init_142 - PHB3 - Timeout Control Register 1 * SW283991: Increase timeouts */ - out_be64(p->regs + PHB_TIMEOUT_CTRL1, 0x1715152016200000); + out_be64(p->regs + PHB_TIMEOUT_CTRL1, 0x1715152016200000UL); /* Init_143 - PHB3 - Timeout Control Register 2 */ - out_be64(p->regs + PHB_TIMEOUT_CTRL2, 0x2320d71600000000); + out_be64(p->regs + PHB_TIMEOUT_CTRL2, 0x2320d71600000000UL); /* Mark the PHB as functional which enables all the various sequences */ p->broken = false; @@ -3089,7 +3089,7 @@ static int64_t load_capp_ucode(struct phb4 *p) /* 0x434150504c494448 = 'CAPPLIDH' in ASCII */ rc = capp_load_ucode(p->chip_id, p->phb.opal_id, p->index, - 0x434150504c494448, PHB4_CAPP_REG_OFFSET(p), + 0x434150504c494448UL, PHB4_CAPP_REG_OFFSET(p), CAPP_APC_MASTER_ARRAY_ADDR_REG, CAPP_APC_MASTER_ARRAY_WRITE_REG, CAPP_SNP_ARRAY_ADDR_REG, @@ -3313,7 +3313,7 @@ static int64_t phb4_creset(struct pci_slot *slot) /* Force fence on the PHB to work around a non-existent PE */ if (!phb4_fenced(p)) xscom_write(p->chip_id, p->pe_stk_xscom + 0x2, - 0x0000002000000000); + 0x0000002000000000UL); /* * Force use of ASB for register access until the PHB has @@ -3331,7 +3331,7 @@ static int64_t phb4_creset(struct pci_slot *slot) /* Actual reset */ xscom_write(p->chip_id, p->pci_stk_xscom + XPEC_PCI_STK_ETU_RESET, - 0x8000000000000000); + 0x8000000000000000UL); /* Read errors in PFIR and NFIR */ xscom_read(p->chip_id, p->pci_stk_xscom + 0x0, &p->pfir_cache); @@ -3344,7 +3344,7 @@ static int64_t phb4_creset(struct pci_slot *slot) // Wait until operations are complete xscom_read(p->chip_id, p->pe_stk_xscom + 0xc, &pbcq_status); - if (!(pbcq_status & 0xC000000000000000)) { + if (!(pbcq_status & 0xC000000000000000UL)) { PHBDBG(p, "CRESET: No pending transactions\n"); /* capp recovery */ @@ -3596,7 +3596,7 @@ static int64_t phb4_eeh_freeze_clear(struct phb *phb, uint64_t pe_number, * explicitely by the user */ err = in_be64(p->regs + PHB_ETU_ERR_SUMMARY); - if (err == 0xffffffffffffffff) { + if (err == 0xffffffffffffffffUL) { if (phb4_fenced(p)) { PHBERR(p, "eeh_freeze_clear on fenced PHB\n"); return OPAL_HARDWARE; @@ -4111,11 +4111,11 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) /* Set PHB mode, HPC Dir State and P9 mode */ xscom_write(p->chip_id, APC_MASTER_CAPI_CTRL + offset, - 0x1772000000000000); + 0x1772000000000000UL); PHBINF(p, "CAPP: port attached\n"); /* Set snoop ttype decoding , dir size to 512K */ - xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, 0x9000000000000000); + xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, 0x9000000000000000UL); /* Use Read Epsilon Tier2 for all scopes. * Set Tier2 Read Epsilon. @@ -4184,24 +4184,24 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) /* Enable epoch timer */ xscom_write(p->chip_id, EPOCH_RECOVERY_TIMERS_CTRL + offset, - 0xC0000000FFF8FFE0); + 0xC0000000FFF8FFE0UL); /* Flush SUE State Map Register */ xscom_write(p->chip_id, FLUSH_SUE_STATE_MAP + offset, - 0x08020A0000000000); + 0x08020A0000000000UL); if (!(p->rev == PHB4_REV_NIMBUS_DD10)) { /* Flush SUE uOP1 Register */ xscom_write(p->chip_id, FLUSH_SUE_UOP1 + offset, - 0xDCE0280428000000); + 0xDCE0280428000000UL); } /* capp owns PHB read buffers */ if (p->index == CAPP0_PHB_INDEX) { /* max PHB read buffers 0-47 */ - reg = 0xFFFFFFFFFFFF0000; + reg = 0xFFFFFFFFFFFF0000UL; if (capp_eng & CAPP_MAX_DMA_READ_ENGINES) - reg = 0xF000000000000000; + reg = 0xF000000000000000UL; xscom_write(p->chip_id, APC_FSM_READ_MASK + offset, reg); xscom_write(p->chip_id, XPT_FSM_RMM + offset, reg); } @@ -4225,13 +4225,13 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) } /* CAPP FIR Action 0 */ - xscom_write(p->chip_id, CAPP_FIR_ACTION0 + offset, 0x0b1c000104060000); + xscom_write(p->chip_id, CAPP_FIR_ACTION0 + offset, 0x0b1c000104060000UL); /* CAPP FIR Action 1 */ - xscom_write(p->chip_id, CAPP_FIR_ACTION1 + offset, 0x2b9c0001240E0000); + xscom_write(p->chip_id, CAPP_FIR_ACTION1 + offset, 0x2b9c0001240E0000UL); /* CAPP FIR MASK */ - xscom_write(p->chip_id, CAPP_FIR_MASK + offset, 0x80031f98d8717000); + xscom_write(p->chip_id, CAPP_FIR_MASK + offset, 0x80031f98d8717000UL); /* Mask the CAPP PSL Credit Timeout Register error */ xscom_write_mask(p->chip_id, CAPP_FIR_MASK + offset, @@ -4330,11 +4330,11 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, xscom_read(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_PBCQ_STAT, ®); - if (!(reg & 0xC000000000000000)) + if (!(reg & 0xC000000000000000UL)) break; time_wait_us(10); } - if (reg & 0xC000000000000000) { + if (reg & 0xC000000000000000UL) { PHBERR(p, "CAPP: Timeout waiting for pending transaction\n"); return OPAL_HARDWARE; } @@ -5356,7 +5356,7 @@ static bool phb4_read_capabilities(struct phb4 *p) /* Grab version and fit it in an int */ val = phb4_read_reg_asb(p, PHB_VERSION); - if (val == 0 || val == 0xffffffffffffffff) { + if (val == 0 || val == 0xffffffffffffffffUL) { PHBERR(p, "Failed to read version, PHB appears broken\n"); return false; } @@ -5366,7 +5366,7 @@ static bool phb4_read_capabilities(struct phb4 *p) /* Read EEH capabilities */ val = in_be64(p->regs + PHB_PHB4_EEH_CAP); - if (val == 0xffffffffffffffff) { + if (val == 0xffffffffffffffffUL) { PHBERR(p, "Failed to read EEH cap, PHB appears broken\n"); return false; } @@ -5385,7 +5385,7 @@ static bool phb4_read_capabilities(struct phb4 *p) p->tvt_size *= 2; val = in_be64(p->regs + PHB_PHB4_IRQ_CAP); - if (val == 0xffffffffffffffff) { + if (val == 0xffffffffffffffffUL) { PHBERR(p, "Failed to read IRQ cap, PHB appears broken\n"); return false; } @@ -5670,10 +5670,10 @@ static const struct irq_source_ops phb4_lsi_ops = { #ifdef HAVE_BIG_ENDIAN static u64 lane_eq_default[8] = { - 0x5454545454545454, 0x5454545454545454, - 0x5454545454545454, 0x5454545454545454, - 0x7777777777777777, 0x7777777777777777, - 0x7777777777777777, 0x7777777777777777 + 0x5454545454545454UL, 0x5454545454545454UL, + 0x5454545454545454UL, 0x5454545454545454UL, + 0x7777777777777777UL, 0x7777777777777777UL, + 0x7777777777777777UL, 0x7777777777777777UL }; #else #error lane_eq_default needs to be big endian (device tree property) @@ -543,8 +543,8 @@ static int xscom_indirect_write_form1(uint32_t gcid, uint64_t pcb_addr, return OPAL_PARAMETER; /* Mangle address and data for form1 */ - addr = (pcb_addr & 0x000ffffffff); - data = (pcb_addr & 0xfff00000000) << 20; + addr = (pcb_addr & 0x000ffffffffUL); + data = (pcb_addr & 0xfff00000000UL) << 20; data |= val; return __xscom_write(gcid, addr, data); } |
