diff options
| author | Michael Neuling <mikey@neuling.org> | 2018-02-22 10:52:18 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-02-22 00:05:20 -0600 |
| commit | 737c0ba3d72b8aab05a765a9fc111a48faac0f75 (patch) | |
| tree | c441f1f220b96a49e7ebeb1e7974a6ab91d5b8c7 /include | |
| parent | 4769f3932c0b93d9e5f929ac8589cef2e4a7d5d6 (diff) | |
| download | blackbird-skiboot-737c0ba3d72b8aab05a765a9fc111a48faac0f75.tar.gz blackbird-skiboot-737c0ba3d72b8aab05a765a9fc111a48faac0f75.zip | |
phb4: Disable lane eq when retrying some nvidia GEN3 devices
This fixes these nvidia cards training at only GEN2 spends rather than
GEN3 by disabling PCIe lane equalisation.
Firstly we check if the card is in a whitelist. If it is and the link
has not trained optimally, retry with lane equalisation off. We do
this on all POWER9 chip revisions since this is a device issue, not
a POWER9 chip issue.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/phb4-regs.h | 4 | ||||
| -rw-r--r-- | include/phb4.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 2dc64fe5..fa585d08 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -301,6 +301,10 @@ #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) +#define PHB_PCIE_DLP_CTL 0x1A78 +#define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4) +#define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5) + #define PHB_PCIE_DLP_TRWCTL 0x1A80 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) diff --git a/include/phb4.h b/include/phb4.h index 6f865b6e..757a3feb 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -264,6 +264,7 @@ struct phb4 { int64_t ecap; /* cached PCI-E cap offset */ int64_t aercap; /* cached AER ecap offset */ const __be64 *lane_eq; + bool lane_eq_en; unsigned int max_link_speed; uint64_t mrt_size; |
